xref: /XiangShan/src/main/scala/system/SoC.scala (revision 799b61e0025fbaab63e978993e47e87546c7730b) 
1package system
2
3import chipsalliance.rocketchip.config.Parameters
4import device.{AXI4Timer, TLTimer}
5import chisel3._
6import chisel3.util._
7import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
8import freechips.rocketchip.tilelink.{TLBuffer, TLFuzzer, TLIdentityNode, TLXbar}
9import utils.DebugIdentityNode
10import xiangshan.{HasXSParameter, XSCore}
11
12
13case class SoCParameters
14(
15  EnableILA: Boolean = false,
16  HasL2Cache: Boolean = false,
17  HasPrefetch: Boolean = false
18)
19
20trait HasSoCParameter extends HasXSParameter{
21  val soc = top.Parameters.get.socParameters
22  val EnableILA = soc.EnableILA
23  val HasL2cache = soc.HasL2Cache
24  val HasPrefetch = soc.HasPrefetch
25}
26
27class ILABundle extends Bundle {}
28
29
30class DummyCore()(implicit p: Parameters) extends LazyModule {
31  val mem = TLFuzzer(nOperations = 10)
32  val mmio = TLFuzzer(nOperations = 10)
33
34  lazy val module = new LazyModuleImp(this){
35
36  }
37}
38
39
40class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
41
42  private val xsCore = LazyModule(new XSCore())
43
44  // only mem and extDev visible externally
45  val mem = xsCore.mem
46  val extDev = TLIdentityNode()
47
48  private val mmioXbar = TLXbar()
49  private val clint = LazyModule(new TLTimer(
50    Seq(AddressSet(0x38000000L, 0x0000ffffL)),
51    sim = !env.FPGAPlatform
52  ))
53
54  mmioXbar :=
55    TLBuffer() :=
56    DebugIdentityNode() :=
57    xsCore.mmio
58
59  clint.node :=
60    mmioXbar
61
62  extDev :=
63    mmioXbar
64
65  lazy val module = new LazyModuleImp(this){
66    val io = IO(new Bundle{
67      val meip = Input(Bool())
68      val ila = if(env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
69    })
70    val mtipSync = clint.module.io.mtip
71    val msipSync = clint.module.io.msip
72    val meipSync = RegNext(RegNext(io.meip))
73    ExcitingUtils.addSource(mtipSync, "mtip")
74    ExcitingUtils.addSource(msipSync, "msip")
75    ExcitingUtils.addSource(meipSync, "meip")
76  }
77
78}
79
80
81//class XSSoc extends Module with HasSoCParameter {
82//  val io = IO(new Bundle{
83//    val mem = new TLCached(l1BusParams)
84//    val mmio = new TLCached(l1BusParams)
85//    val frontend = Flipped(new AXI4) //TODO: do we need it ?
86//    val meip = Input(Bool())
87//    val ila = if (env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
88//  })
89//
90//  val xsCore = Module(new XSCore)
91//
92//  io.frontend <> DontCare
93//
94//  io.mem <> xsCore.io.mem
95//
96//  val addrSpace = List(
97//    (0x40000000L, 0x40000000L), // external devices
98//    (0x38000000L, 0x00010000L)  // CLINT
99//  )
100//  val mmioXbar = Module(new NaiveTL1toN(addrSpace, xsCore.io.mem.params))
101//  mmioXbar.io.in <> xsCore.io.mmio
102//
103//  val extDev = mmioXbar.io.out(0)
104//  val clint = Module(new AXI4Timer(sim = !env.FPGAPlatform))
105//  clint.io.in <> AXI4ToAXI4Lite(MMIOTLToAXI4(mmioXbar.io.out(1)))
106//
107//  io.mmio <> extDev
108//
109//  val mtipSync = clint.io.extra.get.mtip
110//  val meipSync = RegNext(RegNext(io.meip))
111//  ExcitingUtils.addSource(mtipSync, "mtip")
112//  ExcitingUtils.addSource(meipSync, "meip")
113//}
114