xref: /XiangShan/src/main/scala/system/SoC.scala (revision 725e8ddc29ec6e96d16ceac10ae685c894296556) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.debug.DebugModuleKey
25import freechips.rocketchip.devices.tilelink._
26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.PMAConst
35import xiangshan.{DebugOptionsKey, XSTileKey}
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
39import xiangshan.PMParameKey
40
41case object SoCParamsKey extends Field[SoCParameters]
42
43case class SoCParameters
44(
45  EnableILA: Boolean = false,
46  PAddrBits: Int = 48,
47  PmemRanges: Seq[(BigInt, BigInt)] = Seq((0x80000000L, 0x80000000000L)),
48  CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
49  BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
50  PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
51  PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
52  UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
53  extIntrs: Int = 64,
54  L3NBanks: Int = 4,
55  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
56    name = "L3",
57    level = 3,
58    ways = 8,
59    sets = 2048 // 1MB per bank
60  )),
61  OpenLLCParamsOpt: Option[OpenLLCParam] = Some(OpenLLCParam(
62    name = "LLC",
63    ways = 8,
64    sets = 2048,
65    banks = 4,
66    clientCaches = Seq(L2Param())
67  )),
68  XSTopPrefix: Option[String] = None,
69  NodeIDWidthList: Map[String, Int] = Map(
70    "B" -> 7,
71    "E.b" -> 11
72  ),
73  NumHart: Int = 64,
74  NumIRFiles: Int = 7,
75  NumIRSrc: Int = 256,
76  UseXSNoCTop: Boolean = false,
77  IMSICUseTL: Boolean = false,
78  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
79  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
80){
81  // L3 configurations
82  val L3InnerBusWidth = 256
83  val L3BlockSize = 64
84  // on chip network configurations
85  val L3OuterBusWidth = 256
86  val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf)
87}
88
89trait HasSoCParameter {
90  implicit val p: Parameters
91
92  val soc = p(SoCParamsKey)
93  val debugOpts = p(DebugOptionsKey)
94  val tiles = p(XSTileKey)
95  val enableCHI = p(EnableCHI)
96  val issue = p(CHIIssue)
97
98  val NumCores = tiles.size
99  val EnableILA = soc.EnableILA
100
101  // Parameters for trace extension
102  val TraceTraceGroupNum          = tiles.head.traceParams.TraceGroupNum
103  val TraceCauseWidth             = tiles.head.XLEN
104  val TraceTvalWidth              = tiles.head.XLEN
105  val TracePrivWidth              = tiles.head.traceParams.PrivWidth
106  val TraceIaddrWidth             = tiles.head.XLEN
107  val TraceItypeWidth             = tiles.head.traceParams.ItypeWidth
108  val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2)
109  val TraceIlastsizeWidth         = tiles.head.traceParams.IlastsizeWidth
110
111  // L3 configurations
112  val L3InnerBusWidth = soc.L3InnerBusWidth
113  val L3BlockSize = soc.L3BlockSize
114  val L3NBanks = soc.L3NBanks
115
116  // on chip network configurations
117  val L3OuterBusWidth = soc.L3OuterBusWidth
118
119  val NrExtIntr = soc.extIntrs
120
121  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
122
123  val NumIRSrc = soc.NumIRSrc
124
125  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
126    soc.EnableCHIAsyncBridge else None
127  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
128}
129
130trait HasPeripheralRanges {
131  implicit val p: Parameters
132
133  private def soc = p(SoCParamsKey)
134  private def dm = p(DebugModuleKey)
135  private def pmParams = p(PMParameKey)
136
137  private def mmpma = pmParams.mmpma
138
139  def onChipPeripheralRanges: Map[String, AddressSet] = Map(
140    "CLINT" -> soc.CLINTRange,
141    "BEU"   -> soc.BEURange,
142    "PLIC"  -> soc.PLICRange,
143    "PLL"   -> soc.PLLRange,
144    "UART"  -> soc.UARTLiteRange,
145    "DEBUG" -> dm.get.address,
146    "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
147  ) ++ (
148    if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false))
149      Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff))
150    else
151      Map()
152  )
153
154  def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) =>
155    acc.flatMap(_.subtract(x))
156  }
157}
158
159class ILABundle extends Bundle {}
160
161
162abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges {
163  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
164  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
165  val l3_xbar = Option.when(!enableCHI)(TLXbar())
166  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
167
168  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
169}
170
171// We adapt the following three traits from rocket-chip.
172// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
173trait HaveSlaveAXI4Port {
174  this: BaseSoC =>
175
176  val idBits = 14
177
178  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
179    Seq(AXI4MasterParameters(
180      name = "dma",
181      id = IdRange(0, 1 << idBits)
182    ))
183  )))
184
185  if (l3_xbar.isDefined) {
186    val errorDevice = LazyModule(new TLError(
187      params = DevNullParams(
188        address = Seq(AddressSet(0x0, 0x7fffffffL)),
189        maxAtomic = 8,
190        maxTransfer = 64),
191      beatBytes = L3InnerBusWidth / 8
192    ))
193    errorDevice.node :=
194      l3_xbar.get :=
195      TLFIFOFixer() :=
196      TLWidthWidget(32) :=
197      AXI4ToTL() :=
198      AXI4UserYanker(Some(1)) :=
199      AXI4Fragmenter() :=
200      AXI4Buffer() :=
201      AXI4Buffer() :=
202      AXI4IdIndexer(1) :=
203      l3FrontendAXI4Node
204  }
205
206  val dma = InModuleBody {
207    l3FrontendAXI4Node.makeIOs()
208  }
209}
210
211trait HaveAXI4MemPort {
212  this: BaseSoC =>
213  val device = new MemoryDevice
214  // 48-bit physical address
215  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
216  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
217    AXI4SlavePortParameters(
218      slaves = Seq(
219        AXI4SlaveParameters(
220          address = memRange,
221          regionType = RegionType.UNCACHED,
222          executable = true,
223          supportsRead = TransferSizes(1, L3BlockSize),
224          supportsWrite = TransferSizes(1, L3BlockSize),
225          interleavedId = Some(0),
226          resources = device.reg("mem")
227        )
228      ),
229      beatBytes = L3OuterBusWidth / 8,
230      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
231    )
232  ))
233
234  val mem_xbar = TLXbar()
235  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
236  val axi4mem_node = AXI4IdentityNode()
237
238  if (enableCHI) {
239    axi4mem_node :=
240      soc_xbar.get
241  } else {
242    mem_xbar :=*
243      TLBuffer.chainNode(2) :=
244      TLCacheCork() :=
245      l3_mem_pmu :=
246      TLClientsMerger() :=
247      TLXbar() :=*
248      bankedNode.get
249
250    mem_xbar :=
251      TLWidthWidget(8) :=
252      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
253      peripheralXbar.get
254
255    axi4mem_node :=
256      TLToAXI4() :=
257      TLSourceShrinker(64) :=
258      TLWidthWidget(L3OuterBusWidth / 8) :=
259      TLBuffer.chainNode(2) :=
260      mem_xbar
261  }
262
263  memAXI4SlaveNode :=
264    AXI4Buffer() :=
265    AXI4Buffer() :=
266    AXI4Buffer() :=
267    AXI4IdIndexer(idBits = 14) :=
268    AXI4UserYanker() :=
269    AXI4Deinterleaver(L3BlockSize) :=
270    axi4mem_node
271
272  val memory = InModuleBody {
273    memAXI4SlaveNode.makeIOs()
274  }
275}
276
277trait HaveAXI4PeripheralPort { this: BaseSoC =>
278  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
279  val uartParams = AXI4SlaveParameters(
280    address = Seq(soc.UARTLiteRange),
281    regionType = RegionType.UNCACHED,
282    supportsRead = TransferSizes(1, 32),
283    supportsWrite = TransferSizes(1, 32),
284    resources = uartDevice.reg
285  )
286  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
287    Seq(AXI4SlaveParameters(
288      address = peripheralRange,
289      regionType = RegionType.UNCACHED,
290      supportsRead = TransferSizes(1, 32),
291      supportsWrite = TransferSizes(1, 32),
292      interleavedId = Some(0)
293    ), uartParams),
294    beatBytes = 8
295  )))
296
297  val axi4peripheral_node = AXI4IdentityNode()
298  val error_xbar = Option.when(enableCHI)(TLXbar())
299
300  peripheralNode :=
301    AXI4UserYanker() :=
302    AXI4IdIndexer(idBits = 2) :=
303    AXI4Buffer() :=
304    AXI4Buffer() :=
305    AXI4Buffer() :=
306    AXI4Buffer() :=
307    AXI4UserYanker() :=
308    // AXI4Deinterleaver(8) :=
309    axi4peripheral_node
310
311  if (enableCHI) {
312    val error = LazyModule(new TLError(
313      params = DevNullParams(
314        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
315        maxAtomic = 8,
316        maxTransfer = 64),
317      beatBytes = 8
318    ))
319    error.node := error_xbar.get
320    axi4peripheral_node :=
321      AXI4Deinterleaver(8) :=
322      TLToAXI4() :=
323      error_xbar.get :=
324      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
325      TLFIFOFixer() :=
326      TLWidthWidget(L3OuterBusWidth / 8) :=
327      AXI4ToTL() :=
328      AXI4UserYanker() :=
329      soc_xbar.get
330  } else {
331    axi4peripheral_node :=
332      AXI4Deinterleaver(8) :=
333      TLToAXI4() :=
334      TLBuffer.chainNode(3) :=
335      peripheralXbar.get
336  }
337
338  val peripheral = InModuleBody {
339    peripheralNode.makeIOs()
340  }
341
342}
343
344class MemMisc()(implicit p: Parameters) extends BaseSoC
345  with HaveAXI4MemPort
346  with PMAConst
347  with HaveAXI4PeripheralPort
348{
349
350  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
351  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
352
353  val l3_in = TLTempNode()
354  val l3_out = TLTempNode()
355
356  val device_xbar = Option.when(enableCHI)(TLXbar())
357  device_xbar.foreach(_ := error_xbar.get)
358
359  if (l3_banked_xbar.isDefined) {
360    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
361    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
362  }
363  bankedNode match {
364    case Some(bankBinder) =>
365      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
366    case None =>
367  }
368
369  if(soc.L3CacheParamsOpt.isEmpty){
370    l3_out :*= l3_in
371  }
372
373  if (!enableCHI) {
374    for (port <- peripheral_ports.get) {
375      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
376    }
377  }
378
379  core_to_l3_ports.foreach { case _ =>
380    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
381      l3_banked_xbar.get :=*
382        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
383        TLBuffer() :=
384        core_out
385    }
386  }
387
388  val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8))
389  if (enableCHI) { clint.node := device_xbar.get }
390  else { clint.node := peripheralXbar.get }
391
392  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
393    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
394    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
395      val in = IO(Input(Vec(num, Bool())))
396      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
397    }
398    lazy val module = new IntSourceNodeToModuleImp(this)
399  }
400
401  val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8))
402  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
403
404  plic.intnode := plicSource.sourceNode
405  if (enableCHI) { plic.node := device_xbar.get }
406  else { plic.node := peripheralXbar.get }
407
408  val pll_node = TLRegisterNode(
409    address = Seq(soc.PLLRange),
410    device = new SimpleDevice("pll_ctrl", Seq()),
411    beatBytes = 8,
412    concurrency = 1
413  )
414  if (enableCHI) { pll_node := device_xbar.get }
415  else { pll_node := peripheralXbar.get }
416
417  val debugModule = LazyModule(new DebugModule(NumCores)(p))
418  if (enableCHI) {
419    debugModule.debug.node := device_xbar.get
420    // TODO: l3_xbar
421    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
422      error_xbar.get := sb2tl.node
423    }
424  } else {
425    debugModule.debug.node := peripheralXbar.get
426    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
427      l3_xbar.get := TLBuffer() := sb2tl.node
428    }
429  }
430
431  val pma = LazyModule(new TLPMA)
432  if (enableCHI) {
433    pma.node := TLBuffer.chainNode(4) := device_xbar.get
434  } else {
435    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
436  }
437
438  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
439
440    val debug_module_io = IO(new debugModule.DebugModuleIO)
441    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
442    val rtc_clock = IO(Input(Bool()))
443    val pll0_lock = IO(Input(Bool()))
444    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
445    val cacheable_check = IO(new TLPMAIO)
446    val clintTime = IO(Output(ValidIO(UInt(64.W))))
447
448    debugModule.module.io <> debug_module_io
449
450    // sync external interrupts
451    require(plicSource.module.in.length == ext_intrs.getWidth)
452    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
453      val ext_intr_sync = RegInit(0.U(3.W))
454      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
455      plic_in := ext_intr_sync(2)
456    }
457
458    pma.module.io <> cacheable_check
459
460    // positive edge sampling of the lower-speed rtc_clock
461    val rtcTick = RegInit(0.U(3.W))
462    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
463    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
464
465    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
466    val pll_lock = RegNext(next = pll0_lock, init = false.B)
467
468    clintTime := clint.module.io.time
469
470    pll0_ctrl <> VecInit(pll_ctrl_regs)
471
472    pll_node.regmap(
473      0x000 -> RegFieldGroup(
474        "Pll", Some("PLL ctrl regs"),
475        pll_ctrl_regs.zipWithIndex.map{
476          case (r, i) => RegField(32, r, RegFieldDesc(
477            s"PLL_ctrl_$i",
478            desc = s"PLL ctrl register #$i"
479          ))
480        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
481          "PLL_lock",
482          "PLL lock register"
483        ))
484      )
485    )
486  }
487
488  lazy val module = new SoCMiscImp(this)
489}
490
491class SoCMisc()(implicit p: Parameters) extends MemMisc
492  with HaveSlaveAXI4Port
493
494