xref: /XiangShan/src/main/scala/system/SoC.scala (revision 6c199c4e5362394320615e0a3e9de06e7d0c45f9) 
1package system
2
3import noop._
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6import device.AXI4Timer
7
8import chisel3._
9import chisel3.util._
10import chisel3.util.experimental.BoringUtils
11
12trait HasSoCParameter {
13  val EnableILA = false
14  val HasL2cache = true
15  val HasPrefetch = true
16}
17
18class ILABundle extends Bundle {
19  val WBUpc = UInt(32.W)
20  val WBUvalid = UInt(1.W)
21  val WBUrfWen = UInt(1.W)
22  val WBUrfDest = UInt(5.W)
23  val WBUrfData = UInt(64.W)
24  val InstrCnt = UInt(64.W)
25}
26
27class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
28  val io = IO(new Bundle{
29    val mem = new AXI4
30    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
31    val frontend = Flipped(new AXI4)
32    val meip = Input(Bool())
33    val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
34  })
35
36  val noop = Module(new NOOP)
37  val cohMg = Module(new CoherenceManager)
38  val xbar = Module(new SimpleBusCrossbarNto1(2))
39  cohMg.io.in <> noop.io.imem.mem
40  noop.io.dmem.coh <> cohMg.io.out.coh
41  xbar.io.in(0) <> cohMg.io.out.mem
42  xbar.io.in(1) <> noop.io.dmem.mem
43
44  val axi2sb = Module(new AXI42SimpleBusConverter())
45  axi2sb.io.in <> io.frontend
46  noop.io.frontend <> axi2sb.io.out
47
48  if (HasL2cache) {
49    val l2cacheOut = Wire(new SimpleBusC)
50    val l2cacheIn = if (HasPrefetch) {
51      val prefetcher = Module(new Prefetcher)
52      val l2cacheIn = Wire(new SimpleBusUC)
53      prefetcher.io.in <> xbar.io.out.req
54      l2cacheIn.req <> prefetcher.io.out
55      xbar.io.out.resp <> l2cacheIn.resp
56      l2cacheIn
57    } else xbar.io.out
58    val l2Empty = Wire(Bool())
59    l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC) :: Nil, flush = "b00".U, empty = l2Empty, enable = true)(
60      CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
61    io.mem <> l2cacheOut.mem.toAXI4()
62    l2cacheOut.coh.resp.ready := true.B
63    l2cacheOut.coh.req.valid := false.B
64    l2cacheOut.coh.req.bits := DontCare
65  } else {
66    io.mem <> xbar.io.out.toAXI4()
67  }
68
69  noop.io.imem.coh.resp.ready := true.B
70  noop.io.imem.coh.req.valid := false.B
71  noop.io.imem.coh.req.bits := DontCare
72
73  val addrSpace = List(
74    (0x40000000L, 0x08000000L), // external devices
75    (0x48000000L, 0x00010000L)  // CLINT
76  )
77  val mmioXbar = Module(new SimpleBusCrossbar1toN(addrSpace))
78  mmioXbar.io.in <> noop.io.mmio
79
80  val extDev = mmioXbar.io.out(0)
81  val clint = Module(new AXI4Timer(sim = !p.FPGAPlatform))
82  clint.io.in <> mmioXbar.io.out(1).toAXI4Lite()
83  if (p.FPGAPlatform) io.mmio <> extDev.toAXI4Lite()
84  else io.mmio <> extDev
85
86  val mtipSync = clint.io.extra.get.mtip
87  val meipSync = RegNext(RegNext(io.meip))
88  BoringUtils.addSource(mtipSync, "mtip")
89  BoringUtils.addSource(meipSync, "meip")
90
91  // ILA
92  if (p.FPGAPlatform) {
93    def BoringUtilsConnect(sink: UInt, id: String) {
94      val temp = WireInit(0.U(64.W))
95      BoringUtils.addSink(temp, id)
96      sink := temp
97    }
98
99    val dummy = WireInit(0.U.asTypeOf(new ILABundle))
100    val ila = io.ila.getOrElse(dummy)
101    BoringUtilsConnect(ila.WBUpc      ,"ilaWBUpc")
102    BoringUtilsConnect(ila.WBUvalid   ,"ilaWBUvalid")
103    BoringUtilsConnect(ila.WBUrfWen   ,"ilaWBUrfWen")
104    BoringUtilsConnect(ila.WBUrfDest  ,"ilaWBUrfDest")
105    BoringUtilsConnect(ila.WBUrfData  ,"ilaWBUrfData")
106    BoringUtilsConnect(ila.InstrCnt   ,"ilaInstrCnt")
107  }
108}
109