xref: /XiangShan/src/main/scala/system/SoC.scala (revision 68eeafa8a2229450b289b44a3e3644291d5b8e3e) 
1package system
2
3import noop.{Cache,CacheConfig}
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6import device.AXI4Timer
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10import xiangshan.{XSConfig, XSCore}
11
12trait HasSoCParameter {
13  val EnableILA = false
14  val HasL2cache = false
15  val HasPrefetch = false
16}
17
18class ILABundle extends Bundle {}
19
20class XSSoc(implicit val p: XSConfig) extends Module with HasSoCParameter {
21  val io = IO(new Bundle{
22    val mem = new AXI4
23    val mmio = if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC }
24    val frontend = Flipped(new AXI4)
25    val meip = Input(Bool())
26    val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
27  })
28
29  val xsCore = Module(new XSCore)
30  val cohMg = Module(new CoherenceManager)
31  val xbar = Module(new SimpleBusCrossbarNto1(2))
32  cohMg.io.in <> xsCore.io.imem.mem
33  xsCore.io.dmem.coh <> cohMg.io.out.coh
34  xbar.io.in(0) <> cohMg.io.out.mem
35  xbar.io.in(1) <> xsCore.io.dmem.mem
36
37  val axi2sb = Module(new AXI42SimpleBusConverter())
38  axi2sb.io.in <> io.frontend
39  xsCore.io.frontend <> axi2sb.io.out
40
41  if (HasL2cache) {
42    val l2cacheOut = Wire(new SimpleBusC)
43    val l2cacheIn = if (HasPrefetch) {
44      val prefetcher = Module(new Prefetcher)
45      val l2cacheIn = Wire(new SimpleBusUC)
46      prefetcher.io.in <> xbar.io.out.req
47      l2cacheIn.req <> prefetcher.io.out
48      xbar.io.out.resp <> l2cacheIn.resp
49      l2cacheIn
50    } else xbar.io.out
51    val l2Empty = Wire(Bool())
52    l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC) :: Nil, flush = "b00".U, empty = l2Empty, enable = true)(
53      CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
54    io.mem <> l2cacheOut.mem.toAXI4()
55    l2cacheOut.coh.resp.ready := true.B
56    l2cacheOut.coh.req.valid := false.B
57    l2cacheOut.coh.req.bits := DontCare
58  } else {
59    io.mem <> xbar.io.out.toAXI4()
60  }
61  xsCore.io.imem.coh.resp.ready := true.B
62  xsCore.io.imem.coh.req.valid := false.B
63  xsCore.io.imem.coh.req.bits := DontCare
64
65  val addrSpace = List(
66    (0x40000000L, 0x40000000L), // external devices
67    (0x38000000L, 0x00010000L)  // CLINT
68  )
69  val mmioXbar = Module(new SimpleBusCrossbar1toN(addrSpace))
70  mmioXbar.io.in <> xsCore.io.mmio
71
72  val extDev = mmioXbar.io.out(0)
73  val clint = Module(new AXI4Timer(sim = !p.FPGAPlatform))
74  clint.io.in <> mmioXbar.io.out(1).toAXI4Lite()
75  if (p.FPGAPlatform) io.mmio <> extDev.toAXI4Lite()
76  else io.mmio <> extDev
77
78  val mtipSync = clint.io.extra.get.mtip
79  val meipSync = RegNext(RegNext(io.meip))
80  BoringUtils.addSource(mtipSync, "mtip")
81  BoringUtils.addSource(meipSync, "meip")
82}
83