1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package system 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import device.{DebugModule, TLPMA, TLPMAIO, AXI4MemEncrypt} 23import freechips.rocketchip.amba.axi4._ 24import freechips.rocketchip.devices.debug.DebugModuleKey 25import freechips.rocketchip.devices.tilelink._ 26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes} 27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} 28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} 29import freechips.rocketchip.tilelink._ 30import freechips.rocketchip.util.AsyncQueueParams 31import huancun._ 32import top.BusPerfMonitor 33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger} 34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst} 35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey} 36import coupledL2.{EnableCHI, L2Param} 37import coupledL2.tl2chi.CHIIssue 38import openLLC.OpenLLCParam 39 40case object SoCParamsKey extends Field[SoCParameters] 41case object CVMParamskey extends Field[CVMParameters] 42 43case class CVMParameters 44( 45 MEMENCRange: AddressSet = AddressSet(0x38030000L, 0xfff), 46 KeyIDBits: Int = 0, 47 MemencPipes: Int = 4, 48 HasMEMencryption: Boolean = false, 49 HasDelayNoencryption: Boolean = false, // Test specific 50) 51 52case class SoCParameters 53( 54 EnableILA: Boolean = false, 55 PAddrBits: Int = 48, 56 PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)), 57 PMAConfigs: Seq[PMAConfigEntry] = Seq( 58 PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3), 59 PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true), 60 PMAConfigEntry(0x80000000L, a = 1, w = true, r = true), 61 PMAConfigEntry(0x3A000000L, a = 1), 62 PMAConfigEntry(0x39002000L, a = 1, w = true, r = true), 63 PMAConfigEntry(0x39000000L, a = 1, w = true, r = true), 64 PMAConfigEntry(0x38022000L, a = 1, w = true, r = true), 65 PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true), 66 PMAConfigEntry(0x38020000L, a = 1, w = true, r = true), 67 PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable? 68 PMAConfigEntry(0x30010000L, a = 1, w = true, r = true), 69 PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true), 70 PMAConfigEntry(0x10000000L, a = 1, w = true, r = true), 71 PMAConfigEntry(0) 72 ), 73 CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1), 74 BEURange: AddressSet = AddressSet(0x38010000L, 0xfff), 75 PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1), 76 PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff), 77 UARTLiteForDTS: Boolean = true, // should be false in SimMMIO 78 extIntrs: Int = 64, 79 L3NBanks: Int = 4, 80 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 81 name = "L3", 82 level = 3, 83 ways = 8, 84 sets = 2048 // 1MB per bank 85 )), 86 OpenLLCParamsOpt: Option[OpenLLCParam] = None, 87 XSTopPrefix: Option[String] = None, 88 NodeIDWidthList: Map[String, Int] = Map( 89 "B" -> 7, 90 "C" -> 9, 91 "E.b" -> 11 92 ), 93 NumHart: Int = 64, 94 NumIRFiles: Int = 7, 95 NumIRSrc: Int = 256, 96 UseXSNoCTop: Boolean = false, 97 UseXSNoCDiffTop: Boolean = false, 98 UseXSTileDiffTop: Boolean = false, 99 IMSICUseTL: Boolean = false, 100 SeperateDMBus: Boolean = false, 101 EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)), 102 EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)), 103 EnableDMAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)), 104 WFIClockGate: Boolean = false, 105 EnablePowerDown: Boolean = false 106){ 107 require( 108 L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty, 109 "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined" 110 ) 111 // L3 configurations 112 val L3InnerBusWidth = 256 113 val L3BlockSize = 64 114 // on chip network configurations 115 val L3OuterBusWidth = 256 116 val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf) 117} 118 119trait HasSoCParameter { 120 implicit val p: Parameters 121 122 val soc = p(SoCParamsKey) 123 val cvm = p(CVMParamskey) 124 val debugOpts = p(DebugOptionsKey) 125 val tiles = p(XSTileKey) 126 val enableCHI = p(EnableCHI) 127 val issue = p(CHIIssue) 128 129 val NumCores = tiles.size 130 val EnableILA = soc.EnableILA 131 132 // Parameters for trace extension 133 val TraceTraceGroupNum = tiles.head.traceParams.TraceGroupNum 134 val TraceCauseWidth = tiles.head.XLEN 135 val TraceTvalWidth = tiles.head.traceParams.IaddrWidth 136 val TracePrivWidth = tiles.head.traceParams.PrivWidth 137 val TraceIaddrWidth = tiles.head.traceParams.IaddrWidth 138 val TraceItypeWidth = tiles.head.traceParams.ItypeWidth 139 val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2) 140 val TraceIlastsizeWidth = tiles.head.traceParams.IlastsizeWidth 141 142 // L3 configurations 143 val L3InnerBusWidth = soc.L3InnerBusWidth 144 val L3BlockSize = soc.L3BlockSize 145 val L3NBanks = soc.L3NBanks 146 147 // on chip network configurations 148 val L3OuterBusWidth = soc.L3OuterBusWidth 149 150 val NrExtIntr = soc.extIntrs 151 152 val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles 153 154 val NumIRSrc = soc.NumIRSrc 155 156 val SeperateDMBus = soc.SeperateDMBus 157 158 val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined) 159 soc.EnableCHIAsyncBridge else None 160 val EnableClintAsyncBridge = soc.EnableClintAsyncBridge 161 val EnableDMAsyncBridge = if (SeperateDMBus && soc.EnableDMAsyncBridge.isDefined) 162 soc.EnableDMAsyncBridge else None 163 164 val WFIClockGate = soc.WFIClockGate 165 val EnablePowerDown = soc.EnablePowerDown 166 167 def HasMEMencryption = cvm.HasMEMencryption 168 require((cvm.HasMEMencryption && (cvm.KeyIDBits > 0)) || (!cvm.HasMEMencryption && (cvm.KeyIDBits == 0)), 169 "HasMEMencryption most set with KeyIDBits > 0") 170} 171 172trait HasPeripheralRanges { 173 implicit val p: Parameters 174 175 private def cvm = p(CVMParamskey) 176 private def soc = p(SoCParamsKey) 177 private def dm = p(DebugModuleKey) 178 private def pmParams = p(PMParameKey) 179 180 private def mmpma = pmParams.mmpma 181 182 def onChipPeripheralRanges: Map[String, AddressSet] = Map( 183 "CLINT" -> soc.CLINTRange, 184 "BEU" -> soc.BEURange, 185 "PLIC" -> soc.PLICRange, 186 "PLL" -> soc.PLLRange, 187 "UART" -> soc.UARTLiteRange, 188 "DEBUG" -> dm.get.address, 189 "MMPMA" -> AddressSet(mmpma.address, mmpma.mask) 190 ) ++ ( 191 if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false)) 192 Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff)) 193 else 194 Map() 195 ) ++ ( 196 if (cvm.HasMEMencryption) 197 Map("MEMENC" -> cvm.MEMENCRange) 198 else 199 Map() 200 ) 201 202 def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) => 203 acc.flatMap(_.subtract(x)) 204 } 205} 206 207class ILABundle extends Bundle {} 208 209 210abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges { 211 val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize)) 212 val peripheralXbar = Option.when(!enableCHI)(TLXbar()) 213 val l3_xbar = Option.when(!enableCHI)(TLXbar()) 214 val l3_banked_xbar = Option.when(!enableCHI)(TLXbar()) 215 216 val soc_xbar = Option.when(enableCHI)(AXI4Xbar()) 217} 218 219// We adapt the following three traits from rocket-chip. 220// Source: rocket-chip/src/main/scala/subsystem/Ports.scala 221trait HaveSlaveAXI4Port { 222 this: BaseSoC => 223 224 val idBits = 14 225 226 val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters( 227 Seq(AXI4MasterParameters( 228 name = "dma", 229 id = IdRange(0, 1 << idBits) 230 )) 231 ))) 232 233 if (l3_xbar.isDefined) { 234 val errorDevice = LazyModule(new TLError( 235 params = DevNullParams( 236 address = Seq(AddressSet(0x0, 0x7fffffffL)), 237 maxAtomic = 8, 238 maxTransfer = 64), 239 beatBytes = L3InnerBusWidth / 8 240 )) 241 errorDevice.node := 242 l3_xbar.get := 243 TLFIFOFixer() := 244 TLWidthWidget(32) := 245 AXI4ToTL() := 246 AXI4UserYanker(Some(1)) := 247 AXI4Fragmenter() := 248 AXI4Buffer() := 249 AXI4Buffer() := 250 AXI4IdIndexer(1) := 251 l3FrontendAXI4Node 252 } 253 254 val dma = InModuleBody { 255 l3FrontendAXI4Node.makeIOs() 256 } 257} 258 259trait HaveAXI4MemPort { 260 this: BaseSoC => 261 val device = new MemoryDevice 262 // 48-bit physical address 263 val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL)) 264 val memAXI4SlaveNode = AXI4SlaveNode(Seq( 265 AXI4SlavePortParameters( 266 slaves = Seq( 267 AXI4SlaveParameters( 268 address = memRange, 269 regionType = RegionType.UNCACHED, 270 executable = true, 271 supportsRead = TransferSizes(1, L3BlockSize), 272 supportsWrite = TransferSizes(1, L3BlockSize), 273 interleavedId = Some(0), 274 resources = device.reg("mem") 275 ) 276 ), 277 beatBytes = L3OuterBusWidth / 8, 278 requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey), 279 ) 280 )) 281 282 val mem_xbar = TLXbar() 283 val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true) 284 val axi4mem_node = AXI4IdentityNode() 285 286 if (enableCHI) { 287 axi4mem_node := 288 soc_xbar.get 289 } else { 290 mem_xbar :=* 291 TLBuffer.chainNode(2) := 292 TLCacheCork() := 293 l3_mem_pmu := 294 TLClientsMerger() := 295 TLXbar() :=* 296 bankedNode.get 297 298 mem_xbar := 299 TLWidthWidget(8) := 300 TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) := 301 peripheralXbar.get 302 303 axi4mem_node := 304 TLToAXI4() := 305 TLSourceShrinker(64) := 306 TLWidthWidget(L3OuterBusWidth / 8) := 307 TLBuffer.chainNode(2) := 308 mem_xbar 309 } 310 val axi4memencrpty = Option.when(HasMEMencryption)(LazyModule(new AXI4MemEncrypt(cvm.MEMENCRange))) 311 if (HasMEMencryption) { 312 memAXI4SlaveNode := 313 AXI4Buffer() := 314 AXI4Buffer() := 315 AXI4Buffer() := 316 AXI4IdIndexer(idBits = 14) := 317 AXI4UserYanker() := 318 axi4memencrpty.get.node 319 320 axi4memencrpty.get.node := 321 AXI4Deinterleaver(L3BlockSize) := 322 axi4mem_node 323 } else { 324 memAXI4SlaveNode := 325 AXI4Buffer() := 326 AXI4Buffer() := 327 AXI4Buffer() := 328 AXI4IdIndexer(idBits = 14) := 329 AXI4UserYanker() := 330 AXI4Deinterleaver(L3BlockSize) := 331 axi4mem_node 332 } 333 334 335 val memory = InModuleBody { 336 memAXI4SlaveNode.makeIOs() 337 } 338} 339 340trait HaveAXI4PeripheralPort { this: BaseSoC => 341 val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite")) 342 val uartParams = AXI4SlaveParameters( 343 address = Seq(soc.UARTLiteRange), 344 regionType = RegionType.UNCACHED, 345 supportsRead = TransferSizes(1, 32), 346 supportsWrite = TransferSizes(1, 32), 347 resources = uartDevice.reg 348 ) 349 val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters( 350 Seq(AXI4SlaveParameters( 351 address = peripheralRange, 352 regionType = RegionType.UNCACHED, 353 supportsRead = TransferSizes(1, 32), 354 supportsWrite = TransferSizes(1, 32), 355 interleavedId = Some(0) 356 ), uartParams), 357 beatBytes = 8 358 ))) 359 360 val axi4peripheral_node = AXI4IdentityNode() 361 val error_xbar = Option.when(enableCHI)(TLXbar()) 362 363 peripheralNode := 364 AXI4UserYanker() := 365 AXI4IdIndexer(idBits = 2) := 366 AXI4Buffer() := 367 AXI4Buffer() := 368 AXI4Buffer() := 369 AXI4Buffer() := 370 AXI4UserYanker() := 371 // AXI4Deinterleaver(8) := 372 axi4peripheral_node 373 374 if (enableCHI) { 375 val error = LazyModule(new TLError( 376 params = DevNullParams( 377 address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)), 378 maxAtomic = 8, 379 maxTransfer = 64), 380 beatBytes = 8 381 )) 382 error.node := error_xbar.get 383 axi4peripheral_node := 384 AXI4Deinterleaver(8) := 385 TLToAXI4() := 386 error_xbar.get := 387 TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) := 388 TLFIFOFixer() := 389 TLWidthWidget(L3OuterBusWidth / 8) := 390 AXI4ToTL() := 391 AXI4UserYanker() := 392 soc_xbar.get 393 } else { 394 axi4peripheral_node := 395 AXI4Deinterleaver(8) := 396 TLToAXI4() := 397 TLBuffer.chainNode(3) := 398 peripheralXbar.get 399 } 400 401 val peripheral = InModuleBody { 402 peripheralNode.makeIOs() 403 } 404 405} 406 407class MemMisc()(implicit p: Parameters) extends BaseSoC 408 with HaveAXI4MemPort 409 with PMAConst 410 with HaveAXI4PeripheralPort 411{ 412 413 val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 414 val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 415 416 val l3_in = TLTempNode() 417 val l3_out = TLTempNode() 418 419 val device_xbar = Option.when(enableCHI)(TLXbar()) 420 device_xbar.foreach(_ := error_xbar.get) 421 422 if (l3_banked_xbar.isDefined) { 423 l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get 424 l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get 425 } 426 bankedNode match { 427 case Some(bankBinder) => 428 bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out 429 case None => 430 } 431 432 if(soc.L3CacheParamsOpt.isEmpty){ 433 l3_out :*= l3_in 434 } 435 436 if (!enableCHI) { 437 for (port <- peripheral_ports.get) { 438 peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port 439 } 440 } 441 442 core_to_l3_ports.foreach { case _ => 443 for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){ 444 l3_banked_xbar.get :=* 445 TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=* 446 TLBuffer() := 447 core_out 448 } 449 } 450 451 val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8)) 452 if (enableCHI) { clint.node := device_xbar.get } 453 else { clint.node := peripheralXbar.get } 454 455 class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule { 456 val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1)) 457 class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 458 val in = IO(Input(Vec(num, Bool()))) 459 in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i } 460 } 461 lazy val module = new IntSourceNodeToModuleImp(this) 462 } 463 464 val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8)) 465 val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr)) 466 467 plic.intnode := plicSource.sourceNode 468 if (enableCHI) { plic.node := device_xbar.get } 469 else { plic.node := peripheralXbar.get } 470 471 val pll_node = TLRegisterNode( 472 address = Seq(soc.PLLRange), 473 device = new SimpleDevice("pll_ctrl", Seq()), 474 beatBytes = 8, 475 concurrency = 1 476 ) 477 if (enableCHI) { pll_node := device_xbar.get } 478 else { pll_node := peripheralXbar.get } 479 480 val debugModule = LazyModule(new DebugModule(NumCores)(p)) 481 val debugModuleXbarOpt = Option.when(SeperateDMBus)(TLXbar()) 482 if (enableCHI) { 483 if (SeperateDMBus) { 484 debugModule.debug.node := debugModuleXbarOpt.get 485 } else { 486 debugModule.debug.node := device_xbar.get 487 } 488 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 489 error_xbar.get := sb2tl.node 490 } 491 } else { 492 if (SeperateDMBus) { 493 debugModule.debug.node := debugModuleXbarOpt.get 494 } else { 495 debugModule.debug.node := peripheralXbar.get 496 } 497 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 498 l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node 499 } 500 } 501 502 val pma = LazyModule(new TLPMA) 503 if (enableCHI) { 504 pma.node := TLBuffer.chainNode(4) := device_xbar.get 505 if (HasMEMencryption) { 506 axi4memencrpty.get.ctrl_node := TLToAPB() := device_xbar.get 507 } 508 } else { 509 pma.node := TLBuffer.chainNode(4) := peripheralXbar.get 510 if (HasMEMencryption) { 511 axi4memencrpty.get.ctrl_node := TLToAPB() := peripheralXbar.get 512 } 513 } 514 515 class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 516 517 val debug_module_io = IO(new debugModule.DebugModuleIO) 518 val ext_intrs = IO(Input(UInt(NrExtIntr.W))) 519 val rtc_clock = IO(Input(Bool())) 520 val pll0_lock = IO(Input(Bool())) 521 val pll0_ctrl = IO(Output(Vec(6, UInt(32.W)))) 522 val cacheable_check = IO(new TLPMAIO) 523 val clintTime = IO(Output(ValidIO(UInt(64.W)))) 524 525 debugModule.module.io <> debug_module_io 526 527 // sync external interrupts 528 require(plicSource.module.in.length == ext_intrs.getWidth) 529 for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) { 530 val ext_intr_sync = RegInit(0.U(3.W)) 531 ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt) 532 plic_in := ext_intr_sync(2) 533 } 534 535 pma.module.io <> cacheable_check 536 537 if (HasMEMencryption) { 538 val cnt = Counter(true.B, 8)._1 539 axi4memencrpty.get.module.io.random_val := axi4memencrpty.get.module.io.random_req && cnt(2).asBool 540 axi4memencrpty.get.module.io.random_data := cnt(0).asBool 541 } 542 // positive edge sampling of the lower-speed rtc_clock 543 val rtcTick = RegInit(0.U(3.W)) 544 rtcTick := Cat(rtcTick(1, 0), rtc_clock) 545 clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2) 546 547 val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) } 548 val pll_lock = RegNext(next = pll0_lock, init = false.B) 549 550 clintTime := clint.module.io.time 551 552 pll0_ctrl <> VecInit(pll_ctrl_regs) 553 554 pll_node.regmap( 555 0x000 -> RegFieldGroup( 556 "Pll", Some("PLL ctrl regs"), 557 pll_ctrl_regs.zipWithIndex.map{ 558 case (r, i) => RegField(32, r, RegFieldDesc( 559 s"PLL_ctrl_$i", 560 desc = s"PLL ctrl register #$i" 561 )) 562 } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc( 563 "PLL_lock", 564 "PLL lock register" 565 )) 566 ) 567 ) 568 } 569 570 lazy val module = new SoCMiscImp(this) 571} 572 573class SoCMisc()(implicit p: Parameters) extends MemMisc 574 with HaveSlaveAXI4Port 575 576