xref: /XiangShan/src/main/scala/system/SoC.scala (revision 4d7fbe778bc54b333559f0b1311175ae8693f181) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO, AXI4MemEncrypt}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.debug.DebugModuleKey
25import freechips.rocketchip.devices.tilelink._
26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst}
35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey}
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
39
40case object SoCParamsKey extends Field[SoCParameters]
41case object CVMParamskey extends Field[CVMParameters]
42
43case class CVMParameters
44(
45  MEMENCRange: AddressSet = AddressSet(0x38030000L, 0xfff),
46  KeyIDBits: Int = 0,
47  MemencPipes: Int = 4,
48  HasMEMencryption: Boolean = false,
49  HasDelayNoencryption: Boolean = false, // Test specific
50)
51
52case class SoCParameters
53(
54  EnableILA: Boolean = false,
55  PAddrBits: Int = 48,
56  PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)),
57  PMAConfigs: Seq[PMAConfigEntry] = Seq(
58    PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3),
59    PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true),
60    PMAConfigEntry(0x80000000L, a = 1, w = true, r = true),
61    PMAConfigEntry(0x3A000000L, a = 1),
62    PMAConfigEntry(0x39002000L, a = 1, w = true, r = true),
63    PMAConfigEntry(0x39000000L, a = 1, w = true, r = true),
64    PMAConfigEntry(0x38022000L, a = 1, w = true, r = true),
65    PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true),
66    PMAConfigEntry(0x38020000L, a = 1, w = true, r = true),
67    PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable?
68    PMAConfigEntry(0x30010000L, a = 1, w = true, r = true),
69    PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true),
70    PMAConfigEntry(0x10000000L, a = 1, w = true, r = true),
71    PMAConfigEntry(0)
72  ),
73  CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
74  BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
75  PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
76  PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
77  UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
78  extIntrs: Int = 64,
79  L3NBanks: Int = 4,
80  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
81    name = "L3",
82    level = 3,
83    ways = 8,
84    sets = 2048 // 1MB per bank
85  )),
86  OpenLLCParamsOpt: Option[OpenLLCParam] = None,
87  XSTopPrefix: Option[String] = None,
88  NodeIDWidthList: Map[String, Int] = Map(
89    "B" -> 7,
90    "C" -> 9,
91    "E.b" -> 11
92  ),
93  NumHart: Int = 64,
94  NumIRFiles: Int = 7,
95  NumIRSrc: Int = 256,
96  UseXSNoCTop: Boolean = false,
97  UseXSNoCDiffTop: Boolean = false,
98  UseXSTileDiffTop: Boolean = false,
99  IMSICBusType: device.IMSICBusType.Value = device.IMSICBusType.AXI,
100  IMSICParams: aia.IMSICParams = aia.IMSICParams(
101    imsicIntSrcWidth = 8,
102    mAddr = 0x3A800000,
103    sgAddr = 0x3B000000,
104    geilen = 5,
105    vgeinWidth = 6,
106    iselectWidth = 12,
107    EnableImsicAsyncBridge = true,
108    HasTEEIMSIC = false
109  ),
110  SeperateDMBus: Boolean = false,
111  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
112  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)),
113  EnableDMAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)),
114  WFIClockGate: Boolean = false,
115  EnablePowerDown: Boolean = false
116){
117  require(
118    L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty,
119    "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined"
120  )
121  // L3 configurations
122  val L3InnerBusWidth = 256
123  val L3BlockSize = 64
124  // on chip network configurations
125  val L3OuterBusWidth = 256
126  val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf)
127}
128
129trait HasSoCParameter {
130  implicit val p: Parameters
131
132  val soc = p(SoCParamsKey)
133  val cvm = p(CVMParamskey)
134  val debugOpts = p(DebugOptionsKey)
135  val tiles = p(XSTileKey)
136  val enableCHI = p(EnableCHI)
137  val issue = p(CHIIssue)
138
139  val NumCores = tiles.size
140  val EnableILA = soc.EnableILA
141
142  // Parameters for trace extension
143  val TraceTraceGroupNum          = tiles.head.traceParams.TraceGroupNum
144  val TraceCauseWidth             = tiles.head.XLEN
145  val TraceTvalWidth              = tiles.head.traceParams.IaddrWidth
146  val TracePrivWidth              = tiles.head.traceParams.PrivWidth
147  val TraceIaddrWidth             = tiles.head.traceParams.IaddrWidth
148  val TraceItypeWidth             = tiles.head.traceParams.ItypeWidth
149  val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2)
150  val TraceIlastsizeWidth         = tiles.head.traceParams.IlastsizeWidth
151
152  // L3 configurations
153  val L3InnerBusWidth = soc.L3InnerBusWidth
154  val L3BlockSize = soc.L3BlockSize
155  val L3NBanks = soc.L3NBanks
156
157  // on chip network configurations
158  val L3OuterBusWidth = soc.L3OuterBusWidth
159
160  val NrExtIntr = soc.extIntrs
161
162  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
163
164  val NumIRSrc = soc.NumIRSrc
165
166  val SeperateDMBus = soc.SeperateDMBus
167
168  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
169    soc.EnableCHIAsyncBridge else None
170  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
171  val EnableDMAsyncBridge = if (SeperateDMBus && soc.EnableDMAsyncBridge.isDefined)
172    soc.EnableDMAsyncBridge else None
173
174  val WFIClockGate = soc.WFIClockGate
175  val EnablePowerDown = soc.EnablePowerDown
176
177  def HasMEMencryption = cvm.HasMEMencryption
178  require((cvm.HasMEMencryption && (cvm.KeyIDBits > 0)) || (!cvm.HasMEMencryption && (cvm.KeyIDBits == 0)),
179    "HasMEMencryption most set with KeyIDBits > 0")
180}
181
182trait HasPeripheralRanges {
183  implicit val p: Parameters
184
185  private def cvm = p(CVMParamskey)
186  private def soc = p(SoCParamsKey)
187  private def dm = p(DebugModuleKey)
188  private def pmParams = p(PMParameKey)
189
190  private def mmpma = pmParams.mmpma
191
192  def onChipPeripheralRanges: Map[String, AddressSet] = Map(
193    "CLINT" -> soc.CLINTRange,
194    "BEU"   -> soc.BEURange,
195    "PLIC"  -> soc.PLICRange,
196    "PLL"   -> soc.PLLRange,
197    "UART"  -> soc.UARTLiteRange,
198    "DEBUG" -> dm.get.address,
199    "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
200  ) ++ (
201    if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false))
202      Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff))
203    else
204      Map()
205  ) ++ (
206    if (cvm.HasMEMencryption)
207      Map("MEMENC"  -> cvm.MEMENCRange)
208    else
209      Map()
210  )
211
212  def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) =>
213    acc.flatMap(_.subtract(x))
214  }
215}
216
217class ILABundle extends Bundle {}
218
219
220abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges {
221  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
222  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
223  val l3_xbar = Option.when(!enableCHI)(TLXbar())
224  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
225
226  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
227}
228
229// We adapt the following three traits from rocket-chip.
230// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
231trait HaveSlaveAXI4Port {
232  this: BaseSoC =>
233
234  val idBits = 14
235
236  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
237    Seq(AXI4MasterParameters(
238      name = "dma",
239      id = IdRange(0, 1 << idBits)
240    ))
241  )))
242
243  if (l3_xbar.isDefined) {
244    val errorDevice = LazyModule(new TLError(
245      params = DevNullParams(
246        address = Seq(AddressSet(0x0, 0x7fffffffL)),
247        maxAtomic = 8,
248        maxTransfer = 64),
249      beatBytes = L3InnerBusWidth / 8
250    ))
251    errorDevice.node :=
252      l3_xbar.get :=
253      TLFIFOFixer() :=
254      TLWidthWidget(32) :=
255      AXI4ToTL() :=
256      AXI4UserYanker(Some(1)) :=
257      AXI4Fragmenter() :=
258      AXI4Buffer() :=
259      AXI4Buffer() :=
260      AXI4IdIndexer(1) :=
261      l3FrontendAXI4Node
262  }
263
264  val dma = InModuleBody {
265    l3FrontendAXI4Node.makeIOs()
266  }
267}
268
269trait HaveAXI4MemPort {
270  this: BaseSoC =>
271  val device = new MemoryDevice
272  // 48-bit physical address
273  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
274  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
275    AXI4SlavePortParameters(
276      slaves = Seq(
277        AXI4SlaveParameters(
278          address = memRange,
279          regionType = RegionType.UNCACHED,
280          executable = true,
281          supportsRead = TransferSizes(1, L3BlockSize),
282          supportsWrite = TransferSizes(1, L3BlockSize),
283          interleavedId = Some(0),
284          resources = device.reg("mem")
285        )
286      ),
287      beatBytes = L3OuterBusWidth / 8,
288      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
289    )
290  ))
291
292  val mem_xbar = TLXbar()
293  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
294  val axi4mem_node = AXI4IdentityNode()
295
296  if (enableCHI) {
297    axi4mem_node :=
298      soc_xbar.get
299  } else {
300    mem_xbar :=*
301      TLBuffer.chainNode(2) :=
302      TLCacheCork() :=
303      l3_mem_pmu :=
304      TLClientsMerger() :=
305      TLXbar() :=*
306      bankedNode.get
307
308    mem_xbar :=
309      TLWidthWidget(8) :=
310      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
311      peripheralXbar.get
312
313    axi4mem_node :=
314      TLToAXI4() :=
315      TLSourceShrinker(64) :=
316      TLWidthWidget(L3OuterBusWidth / 8) :=
317      TLBuffer.chainNode(2) :=
318      mem_xbar
319  }
320  val axi4memencrpty = Option.when(HasMEMencryption)(LazyModule(new AXI4MemEncrypt(cvm.MEMENCRange)))
321  if (HasMEMencryption) {
322    memAXI4SlaveNode :=
323      AXI4Buffer() :=
324      AXI4Buffer() :=
325      AXI4Buffer() :=
326      AXI4IdIndexer(idBits = 14) :=
327      AXI4UserYanker() :=
328      axi4memencrpty.get.node
329
330    axi4memencrpty.get.node :=
331      AXI4Deinterleaver(L3BlockSize) :=
332      axi4mem_node
333  } else {
334    memAXI4SlaveNode :=
335      AXI4Buffer() :=
336      AXI4Buffer() :=
337      AXI4Buffer() :=
338      AXI4IdIndexer(idBits = 14) :=
339      AXI4UserYanker() :=
340      AXI4Deinterleaver(L3BlockSize) :=
341      axi4mem_node
342  }
343
344
345  val memory = InModuleBody {
346    memAXI4SlaveNode.makeIOs()
347  }
348}
349
350trait HaveAXI4PeripheralPort { this: BaseSoC =>
351  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
352  val uartParams = AXI4SlaveParameters(
353    address = Seq(soc.UARTLiteRange),
354    regionType = RegionType.UNCACHED,
355    supportsRead = TransferSizes(1, 32),
356    supportsWrite = TransferSizes(1, 32),
357    resources = uartDevice.reg
358  )
359  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
360    Seq(AXI4SlaveParameters(
361      address = peripheralRange,
362      regionType = RegionType.UNCACHED,
363      supportsRead = TransferSizes(1, 32),
364      supportsWrite = TransferSizes(1, 32),
365      interleavedId = Some(0)
366    ), uartParams),
367    beatBytes = 8
368  )))
369
370  val axi4peripheral_node = AXI4IdentityNode()
371  val error_xbar = Option.when(enableCHI)(TLXbar())
372
373  peripheralNode :=
374    AXI4UserYanker() :=
375    AXI4IdIndexer(idBits = 2) :=
376    AXI4Buffer() :=
377    AXI4Buffer() :=
378    AXI4Buffer() :=
379    AXI4Buffer() :=
380    AXI4UserYanker() :=
381    // AXI4Deinterleaver(8) :=
382    axi4peripheral_node
383
384  if (enableCHI) {
385    val error = LazyModule(new TLError(
386      params = DevNullParams(
387        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
388        maxAtomic = 8,
389        maxTransfer = 64),
390      beatBytes = 8
391    ))
392    error.node := error_xbar.get
393    axi4peripheral_node :=
394      AXI4Deinterleaver(8) :=
395      TLToAXI4() :=
396      error_xbar.get :=
397      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
398      TLFIFOFixer() :=
399      TLWidthWidget(L3OuterBusWidth / 8) :=
400      AXI4ToTL() :=
401      AXI4UserYanker() :=
402      soc_xbar.get
403  } else {
404    axi4peripheral_node :=
405      AXI4Deinterleaver(8) :=
406      TLToAXI4() :=
407      TLBuffer.chainNode(3) :=
408      peripheralXbar.get
409  }
410
411  val peripheral = InModuleBody {
412    peripheralNode.makeIOs()
413  }
414
415}
416
417class MemMisc()(implicit p: Parameters) extends BaseSoC
418  with HaveAXI4MemPort
419  with PMAConst
420  with HaveAXI4PeripheralPort
421{
422
423  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
424  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
425
426  val l3_in = TLTempNode()
427  val l3_out = TLTempNode()
428
429  val device_xbar = Option.when(enableCHI)(TLXbar())
430  device_xbar.foreach(_ := error_xbar.get)
431
432  if (l3_banked_xbar.isDefined) {
433    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
434    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
435  }
436  bankedNode match {
437    case Some(bankBinder) =>
438      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
439    case None =>
440  }
441
442  if(soc.L3CacheParamsOpt.isEmpty){
443    l3_out :*= l3_in
444  }
445
446  if (!enableCHI) {
447    for (port <- peripheral_ports.get) {
448      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
449    }
450  }
451
452  core_to_l3_ports.foreach { case _ =>
453    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
454      l3_banked_xbar.get :=*
455        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
456        TLBuffer() :=
457        core_out
458    }
459  }
460
461  val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8))
462  if (enableCHI) { clint.node := device_xbar.get }
463  else { clint.node := peripheralXbar.get }
464
465  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
466    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
467    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
468      val in = IO(Input(Vec(num, Bool())))
469      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
470    }
471    lazy val module = new IntSourceNodeToModuleImp(this)
472  }
473
474  val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8))
475  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
476
477  plic.intnode := plicSource.sourceNode
478  if (enableCHI) { plic.node := device_xbar.get }
479  else { plic.node := peripheralXbar.get }
480
481  val pll_node = TLRegisterNode(
482    address = Seq(soc.PLLRange),
483    device = new SimpleDevice("pll_ctrl", Seq()),
484    beatBytes = 8,
485    concurrency = 1
486  )
487  if (enableCHI) { pll_node := device_xbar.get }
488  else { pll_node := peripheralXbar.get }
489
490  val debugModule = LazyModule(new DebugModule(NumCores)(p))
491  val debugModuleXbarOpt = Option.when(SeperateDMBus)(TLXbar())
492  if (enableCHI) {
493    if (SeperateDMBus) {
494      debugModule.debug.node := debugModuleXbarOpt.get
495    } else {
496      debugModule.debug.node := device_xbar.get
497    }
498    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
499      error_xbar.get := sb2tl.node
500    }
501  } else {
502    if (SeperateDMBus) {
503      debugModule.debug.node := debugModuleXbarOpt.get
504    } else {
505      debugModule.debug.node := peripheralXbar.get
506    }
507    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
508      l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node
509    }
510  }
511
512  val pma = LazyModule(new TLPMA)
513  if (enableCHI) {
514    pma.node := TLBuffer.chainNode(4) := device_xbar.get
515    if (HasMEMencryption) {
516      axi4memencrpty.get.ctrl_node := TLToAPB() := device_xbar.get
517    }
518  } else {
519    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
520    if (HasMEMencryption) {
521      axi4memencrpty.get.ctrl_node := TLToAPB() := peripheralXbar.get
522    }
523  }
524
525  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
526
527    val debug_module_io = IO(new debugModule.DebugModuleIO)
528    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
529    val rtc_clock = IO(Input(Bool()))
530    val pll0_lock = IO(Input(Bool()))
531    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
532    val cacheable_check = IO(new TLPMAIO)
533    val clintTime = IO(Output(ValidIO(UInt(64.W))))
534
535    debugModule.module.io <> debug_module_io
536
537    // sync external interrupts
538    require(plicSource.module.in.length == ext_intrs.getWidth)
539    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
540      val ext_intr_sync = RegInit(0.U(3.W))
541      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
542      plic_in := ext_intr_sync(2)
543    }
544
545    pma.module.io <> cacheable_check
546
547    if (HasMEMencryption) {
548      val cnt = Counter(true.B, 8)._1
549      axi4memencrpty.get.module.io.random_val := axi4memencrpty.get.module.io.random_req && cnt(2).asBool
550      axi4memencrpty.get.module.io.random_data := cnt(0).asBool
551    }
552    // positive edge sampling of the lower-speed rtc_clock
553    val rtcTick = RegInit(0.U(3.W))
554    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
555    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
556
557    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
558    val pll_lock = RegNext(next = pll0_lock, init = false.B)
559
560    clintTime := clint.module.io.time
561
562    pll0_ctrl <> VecInit(pll_ctrl_regs)
563
564    pll_node.regmap(
565      0x000 -> RegFieldGroup(
566        "Pll", Some("PLL ctrl regs"),
567        pll_ctrl_regs.zipWithIndex.map{
568          case (r, i) => RegField(32, r, RegFieldDesc(
569            s"PLL_ctrl_$i",
570            desc = s"PLL ctrl register #$i"
571          ))
572        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
573          "PLL_lock",
574          "PLL lock register"
575        ))
576      )
577    )
578  }
579
580  lazy val module = new SoCMiscImp(this)
581}
582
583class SoCMisc()(implicit p: Parameters) extends MemMisc
584  with HaveSlaveAXI4Port
585
586