xref: /XiangShan/src/main/scala/system/SoC.scala (revision 4cd61964efcdce6a4bb26db0fd9474b5ba56a8d7) 
1package system
2
3import noop._
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10
11trait HasSoCParameter {
12  val EnableILA = false
13  val HasL2cache = true
14  val HasPrefetch = false
15}
16
17class ILABundle extends Bundle {
18  val WBUpc = UInt(32.W)
19  val WBUvalid = UInt(1.W)
20  val WBUrfWen = UInt(1.W)
21  val WBUrfDest = UInt(5.W)
22  val WBUrfData = UInt(64.W)
23  val InstrCnt = UInt(64.W)
24}
25
26class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
27  val io = IO(new Bundle{
28    val mem = new AXI4
29    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
30    val mtip = Input(Bool())
31    val meip = Input(Bool())
32    val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
33  })
34
35  val noop = Module(new NOOP)
36
37	val cohMg = Module(new CoherenceManager)
38  val xbar = Module(new SimpleBusCrossbarNto1(2))
39  cohMg.io.in <> noop.io.imem.mem
40  noop.io.dmem.coh <> cohMg.io.out.coh
41  xbar.io.in(0) <> cohMg.io.out.mem
42  xbar.io.in(1) <> noop.io.dmem.mem
43
44  if (HasL2cache) {
45    val l2cacheOut = Wire(new SimpleBusC)
46    if (HasPrefetch) {
47      val prefetcher = Module(new Prefetcher)
48      prefetcher.io.in <> noop.io.prefetchReq
49      val l2cacheIn = Wire(new SimpleBusUC)
50      val l2cacheInReqArb = Module(new Arbiter(chiselTypeOf(noop.io.prefetchReq.bits), 2))
51      l2cacheInReqArb.io.in(0) <> xbar.io.out.req
52      l2cacheInReqArb.io.in(1) <> prefetcher.io.out
53      l2cacheIn.req <> l2cacheInReqArb.io.out
54      xbar.io.out.resp <> l2cacheIn.resp
55      l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(
56        CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
57    } else {
58      l2cacheOut <> Cache(in = xbar.io.out, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(
59        CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
60    }
61    io.mem <> l2cacheOut.mem.toAXI4()
62    l2cacheOut.coh.resp.ready := true.B
63    l2cacheOut.coh.req.valid := false.B
64    l2cacheOut.coh.req.bits := DontCare
65  } else {
66    io.mem <> xbar.io.out.toAXI4()
67  }
68
69  if (!HasPrefetch) {
70    noop.io.prefetchReq.ready := true.B
71  }
72
73  noop.io.imem.coh.resp.ready := true.B
74  noop.io.imem.coh.req.valid := false.B
75  noop.io.imem.coh.req.bits := DontCare
76
77  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
78  else io.mmio <> noop.io.mmio
79
80  val mtipSync = RegNext(RegNext(io.mtip))
81  val meipSync = RegNext(RegNext(io.meip))
82  BoringUtils.addSource(mtipSync, "mtip")
83  BoringUtils.addSource(meipSync, "meip")
84
85  // ILA
86  if (p.FPGAPlatform) {
87    def BoringUtilsConnect(sink: UInt, id: String) {
88      val temp = WireInit(0.U(64.W))
89      BoringUtils.addSink(temp, id)
90      sink := temp
91    }
92
93    val dummy = WireInit(0.U.asTypeOf(new ILABundle))
94    val ila = io.ila.getOrElse(dummy)
95    BoringUtilsConnect(ila.WBUpc      ,"ilaWBUpc")
96    BoringUtilsConnect(ila.WBUvalid   ,"ilaWBUvalid")
97    BoringUtilsConnect(ila.WBUrfWen   ,"ilaWBUrfWen")
98    BoringUtilsConnect(ila.WBUrfDest  ,"ilaWBUrfDest")
99    BoringUtilsConnect(ila.WBUrfData  ,"ilaWBUrfData")
100    BoringUtilsConnect(ila.InstrCnt   ,"ilaInstrCnt")
101  }
102}
103