xref: /XiangShan/src/main/scala/system/SoC.scala (revision 44899926e3f250675dd7170b53c4fdcbc6d40695) 
1package system
2
3import noop._
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10
11trait HasSoCParameter {
12  val EnableILA = false
13  val HasL2cache = true
14  val HasPrefetch = true
15}
16
17class ILABundle extends Bundle {
18  val WBUpc = UInt(32.W)
19  val WBUvalid = UInt(1.W)
20  val WBUrfWen = UInt(1.W)
21  val WBUrfDest = UInt(5.W)
22  val WBUrfData = UInt(64.W)
23  val InstrCnt = UInt(64.W)
24}
25
26class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
27  val io = IO(new Bundle{
28    val mem = new AXI4
29    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
30    val mtip = Input(Bool())
31    val meip = Input(Bool())
32    val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
33  })
34
35  val noop = Module(new NOOP)
36  val cohMg = Module(new CoherenceManager)
37  val xbar = Module(new SimpleBusCrossbarNto1(2))
38  cohMg.io.in <> noop.io.imem.mem
39  noop.io.dmem.coh <> cohMg.io.out.coh
40  xbar.io.in(0) <> cohMg.io.out.mem
41  xbar.io.in(1) <> noop.io.dmem.mem
42
43  if (HasL2cache) {
44    val l2cacheOut = Wire(new SimpleBusC)
45    val l2cacheIn = if (HasPrefetch) {
46      val prefetcher = Module(new Prefetcher)
47      val l2cacheIn = Wire(new SimpleBusUC)
48      prefetcher.io.in <> xbar.io.out.req
49      l2cacheIn.req <> prefetcher.io.out
50      xbar.io.out.resp <> l2cacheIn.resp
51      l2cacheIn
52    } else xbar.io.out
53    val l2Empty = Wire(Bool())
54    l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, empty = l2Empty, enable = true)(
55      CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
56    io.mem <> l2cacheOut.mem.toAXI4()
57    l2cacheOut.coh.resp.ready := true.B
58    l2cacheOut.coh.req.valid := false.B
59    l2cacheOut.coh.req.bits := DontCare
60  } else {
61    io.mem <> xbar.io.out.toAXI4()
62  }
63
64  noop.io.imem.coh.resp.ready := true.B
65  noop.io.imem.coh.req.valid := false.B
66  noop.io.imem.coh.req.bits := DontCare
67
68  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
69  else io.mmio <> noop.io.mmio
70
71  val mtipSync = RegNext(RegNext(io.mtip))
72  val meipSync = RegNext(RegNext(io.meip))
73  BoringUtils.addSource(mtipSync, "mtip")
74  BoringUtils.addSource(meipSync, "meip")
75
76  // ILA
77  if (p.FPGAPlatform) {
78    def BoringUtilsConnect(sink: UInt, id: String) {
79      val temp = WireInit(0.U(64.W))
80      BoringUtils.addSink(temp, id)
81      sink := temp
82    }
83
84    val dummy = WireInit(0.U.asTypeOf(new ILABundle))
85    val ila = io.ila.getOrElse(dummy)
86    BoringUtilsConnect(ila.WBUpc      ,"ilaWBUpc")
87    BoringUtilsConnect(ila.WBUvalid   ,"ilaWBUvalid")
88    BoringUtilsConnect(ila.WBUrfWen   ,"ilaWBUrfWen")
89    BoringUtilsConnect(ila.WBUrfDest  ,"ilaWBUrfDest")
90    BoringUtilsConnect(ila.WBUrfData  ,"ilaWBUrfData")
91    BoringUtilsConnect(ila.InstrCnt   ,"ilaInstrCnt")
92  }
93}
94