1package system 2 3import noop._ 4import bus.axi4.{AXI4, AXI4Lite} 5import bus.simplebus._ 6 7import chisel3._ 8import chisel3.util._ 9import chisel3.util.experimental.BoringUtils 10 11class NOOPSoC(implicit val p: NOOPConfig) extends NOOPModule { 12 val io = IO(new Bundle{ 13 val mem = new AXI4 14 val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC }) 15 val mtip = Input(Bool()) 16 val meip = Input(Bool()) 17 }) 18 19 val noop = Module(new NOOP) 20 21 val cohMg = Module(new CoherenceManager) 22 val xbar = Module(new SimpleBusCrossbarNto1(2)) 23 cohMg.io.in <> noop.io.imem.mem 24 noop.io.dmem.coh <> cohMg.io.out.coh 25 xbar.io.in(0) <> cohMg.io.out.mem 26 xbar.io.in(1) <> noop.io.dmem.mem 27 28 if (HasL2cache) { 29 val l2cacheOut = Wire(new SimpleBusC) 30 if (HasPrefetch) { 31 val prefetcher = Module(new Prefetcher) 32 prefetcher.io.in <> noop.io.prefetchReq 33 val l2cacheIn = Wire(new SimpleBusUC) 34 val l2cacheInReqArb = Module(new Arbiter(chiselTypeOf(noop.io.prefetchReq.bits), 2)) 35 l2cacheInReqArb.io.in(0) <> xbar.io.out.req 36 l2cacheInReqArb.io.in(1) <> prefetcher.io.out 37 l2cacheIn.req <> l2cacheInReqArb.io.out 38 xbar.io.out.resp <> l2cacheIn.resp 39 l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2)) 40 } else { 41 l2cacheOut <> Cache(in = xbar.io.out, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2)) 42 } 43 io.mem <> l2cacheOut.mem.toAXI4() 44 l2cacheOut.coh.resp.ready := true.B 45 l2cacheOut.coh.req.valid := false.B 46 l2cacheOut.coh.req.bits := DontCare 47 } else { 48 io.mem <> xbar.io.out.toAXI4() 49 } 50 51 if (!HasPrefetch) { 52 noop.io.prefetchReq.ready := true.B 53 } 54 55 noop.io.imem.coh.resp.ready := true.B 56 noop.io.imem.coh.req.valid := false.B 57 noop.io.imem.coh.req.bits := DontCare 58 59 if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite() 60 else io.mmio <> noop.io.mmio 61 62 val mtipSync = RegNext(RegNext(io.mtip)) 63 val meipSync = RegNext(RegNext(io.meip)) 64 BoringUtils.addSource(mtipSync, "mtip") 65 BoringUtils.addSource(meipSync, "meip") 66} 67