xref: /XiangShan/src/main/scala/system/SoC.scala (revision 2caa7ef23d5d6566d68f5f98a59dc7ee9066b96a) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO, AXI4MemEncrypt}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.debug.DebugModuleKey
25import freechips.rocketchip.devices.tilelink._
26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst}
35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey}
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
39
40case object SoCParamsKey extends Field[SoCParameters]
41case object CVMParamskey extends Field[CVMParameters]
42
43case class CVMParameters
44(
45  MEMENCRange: AddressSet = AddressSet(0x38030000L, 0xfff),
46  KeyIDBits: Int = 0,
47  MemencPipes: Int = 4,
48  HasMEMencryption: Boolean = false,
49  HasDelayNoencryption: Boolean = false, // Test specific
50)
51
52case class SoCParameters
53(
54  EnableILA: Boolean = false,
55  PAddrBits: Int = 48,
56  PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)),
57  PMAConfigs: Seq[PMAConfigEntry] = Seq(
58    PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3),
59    PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true),
60    PMAConfigEntry(0x80000000L, a = 1, w = true, r = true),
61    PMAConfigEntry(0x3A000000L, a = 1),
62    PMAConfigEntry(0x39002000L, a = 1, w = true, r = true),
63    PMAConfigEntry(0x39000000L, a = 1, w = true, r = true),
64    PMAConfigEntry(0x38022000L, a = 1, w = true, r = true),
65    PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true),
66    PMAConfigEntry(0x38020000L, a = 1, w = true, r = true),
67    PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable?
68    PMAConfigEntry(0x30010000L, a = 1, w = true, r = true),
69    PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true),
70    PMAConfigEntry(0x10000000L, a = 1, w = true, r = true),
71    PMAConfigEntry(0)
72  ),
73  CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
74  BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
75  PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
76  PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
77  UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
78  extIntrs: Int = 64,
79  L3NBanks: Int = 4,
80  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
81    name = "L3",
82    level = 3,
83    ways = 8,
84    sets = 2048 // 1MB per bank
85  )),
86  OpenLLCParamsOpt: Option[OpenLLCParam] = None,
87  XSTopPrefix: Option[String] = None,
88  NodeIDWidthList: Map[String, Int] = Map(
89    "B" -> 7,
90    "C" -> 9,
91    "E.b" -> 11
92  ),
93  NumHart: Int = 64,
94  NumIRFiles: Int = 7,
95  NumIRSrc: Int = 256,
96  UseXSNoCTop: Boolean = false,
97  UseXSNoCDiffTop: Boolean = false,
98  IMSICUseTL: Boolean = false,
99  SeperateDMBus: Boolean = false,
100  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
101  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)),
102  EnableDMAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
103){
104  require(
105    L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty,
106    "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined"
107  )
108  // L3 configurations
109  val L3InnerBusWidth = 256
110  val L3BlockSize = 64
111  // on chip network configurations
112  val L3OuterBusWidth = 256
113  val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf)
114}
115
116trait HasSoCParameter {
117  implicit val p: Parameters
118
119  val soc = p(SoCParamsKey)
120  val cvm = p(CVMParamskey)
121  val debugOpts = p(DebugOptionsKey)
122  val tiles = p(XSTileKey)
123  val enableCHI = p(EnableCHI)
124  val issue = p(CHIIssue)
125
126  val NumCores = tiles.size
127  val EnableILA = soc.EnableILA
128
129  // Parameters for trace extension
130  val TraceTraceGroupNum          = tiles.head.traceParams.TraceGroupNum
131  val TraceCauseWidth             = tiles.head.XLEN
132  val TraceTvalWidth              = tiles.head.traceParams.IaddrWidth
133  val TracePrivWidth              = tiles.head.traceParams.PrivWidth
134  val TraceIaddrWidth             = tiles.head.traceParams.IaddrWidth
135  val TraceItypeWidth             = tiles.head.traceParams.ItypeWidth
136  val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2)
137  val TraceIlastsizeWidth         = tiles.head.traceParams.IlastsizeWidth
138
139  // L3 configurations
140  val L3InnerBusWidth = soc.L3InnerBusWidth
141  val L3BlockSize = soc.L3BlockSize
142  val L3NBanks = soc.L3NBanks
143
144  // on chip network configurations
145  val L3OuterBusWidth = soc.L3OuterBusWidth
146
147  val NrExtIntr = soc.extIntrs
148
149  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
150
151  val NumIRSrc = soc.NumIRSrc
152
153  val SeperateDMBus = soc.SeperateDMBus
154
155  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
156    soc.EnableCHIAsyncBridge else None
157  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
158  val EnableDMAsyncBridge = if (SeperateDMBus && soc.EnableDMAsyncBridge.isDefined)
159    soc.EnableDMAsyncBridge else None
160
161  def HasMEMencryption = cvm.HasMEMencryption
162  require((cvm.HasMEMencryption && (cvm.KeyIDBits > 0)) || (!cvm.HasMEMencryption && (cvm.KeyIDBits == 0)),
163    "HasMEMencryption most set with KeyIDBits > 0")
164}
165
166trait HasPeripheralRanges {
167  implicit val p: Parameters
168
169  private def cvm = p(CVMParamskey)
170  private def soc = p(SoCParamsKey)
171  private def dm = p(DebugModuleKey)
172  private def pmParams = p(PMParameKey)
173
174  private def mmpma = pmParams.mmpma
175
176  def onChipPeripheralRanges: Map[String, AddressSet] = Map(
177    "CLINT" -> soc.CLINTRange,
178    "BEU"   -> soc.BEURange,
179    "PLIC"  -> soc.PLICRange,
180    "PLL"   -> soc.PLLRange,
181    "UART"  -> soc.UARTLiteRange,
182    "DEBUG" -> dm.get.address,
183    "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
184  ) ++ (
185    if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false))
186      Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff))
187    else
188      Map()
189  ) ++ (
190    if (cvm.HasMEMencryption)
191      Map("MEMENC"  -> cvm.MEMENCRange)
192    else
193      Map()
194  )
195
196  def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) =>
197    acc.flatMap(_.subtract(x))
198  }
199}
200
201class ILABundle extends Bundle {}
202
203
204abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges {
205  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
206  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
207  val l3_xbar = Option.when(!enableCHI)(TLXbar())
208  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
209
210  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
211}
212
213// We adapt the following three traits from rocket-chip.
214// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
215trait HaveSlaveAXI4Port {
216  this: BaseSoC =>
217
218  val idBits = 14
219
220  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
221    Seq(AXI4MasterParameters(
222      name = "dma",
223      id = IdRange(0, 1 << idBits)
224    ))
225  )))
226
227  if (l3_xbar.isDefined) {
228    val errorDevice = LazyModule(new TLError(
229      params = DevNullParams(
230        address = Seq(AddressSet(0x0, 0x7fffffffL)),
231        maxAtomic = 8,
232        maxTransfer = 64),
233      beatBytes = L3InnerBusWidth / 8
234    ))
235    errorDevice.node :=
236      l3_xbar.get :=
237      TLFIFOFixer() :=
238      TLWidthWidget(32) :=
239      AXI4ToTL() :=
240      AXI4UserYanker(Some(1)) :=
241      AXI4Fragmenter() :=
242      AXI4Buffer() :=
243      AXI4Buffer() :=
244      AXI4IdIndexer(1) :=
245      l3FrontendAXI4Node
246  }
247
248  val dma = InModuleBody {
249    l3FrontendAXI4Node.makeIOs()
250  }
251}
252
253trait HaveAXI4MemPort {
254  this: BaseSoC =>
255  val device = new MemoryDevice
256  // 48-bit physical address
257  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
258  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
259    AXI4SlavePortParameters(
260      slaves = Seq(
261        AXI4SlaveParameters(
262          address = memRange,
263          regionType = RegionType.UNCACHED,
264          executable = true,
265          supportsRead = TransferSizes(1, L3BlockSize),
266          supportsWrite = TransferSizes(1, L3BlockSize),
267          interleavedId = Some(0),
268          resources = device.reg("mem")
269        )
270      ),
271      beatBytes = L3OuterBusWidth / 8,
272      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
273    )
274  ))
275
276  val mem_xbar = TLXbar()
277  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
278  val axi4mem_node = AXI4IdentityNode()
279
280  if (enableCHI) {
281    axi4mem_node :=
282      soc_xbar.get
283  } else {
284    mem_xbar :=*
285      TLBuffer.chainNode(2) :=
286      TLCacheCork() :=
287      l3_mem_pmu :=
288      TLClientsMerger() :=
289      TLXbar() :=*
290      bankedNode.get
291
292    mem_xbar :=
293      TLWidthWidget(8) :=
294      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
295      peripheralXbar.get
296
297    axi4mem_node :=
298      TLToAXI4() :=
299      TLSourceShrinker(64) :=
300      TLWidthWidget(L3OuterBusWidth / 8) :=
301      TLBuffer.chainNode(2) :=
302      mem_xbar
303  }
304  val axi4memencrpty = Option.when(HasMEMencryption)(LazyModule(new AXI4MemEncrypt(cvm.MEMENCRange)))
305  if (HasMEMencryption) {
306    memAXI4SlaveNode :=
307      AXI4Buffer() :=
308      AXI4Buffer() :=
309      AXI4Buffer() :=
310      AXI4IdIndexer(idBits = 14) :=
311      AXI4UserYanker() :=
312      axi4memencrpty.get.node
313
314    axi4memencrpty.get.node :=
315      AXI4Deinterleaver(L3BlockSize) :=
316      axi4mem_node
317  } else {
318    memAXI4SlaveNode :=
319      AXI4Buffer() :=
320      AXI4Buffer() :=
321      AXI4Buffer() :=
322      AXI4IdIndexer(idBits = 14) :=
323      AXI4UserYanker() :=
324      AXI4Deinterleaver(L3BlockSize) :=
325      axi4mem_node
326  }
327
328
329  val memory = InModuleBody {
330    memAXI4SlaveNode.makeIOs()
331  }
332}
333
334trait HaveAXI4PeripheralPort { this: BaseSoC =>
335  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
336  val uartParams = AXI4SlaveParameters(
337    address = Seq(soc.UARTLiteRange),
338    regionType = RegionType.UNCACHED,
339    supportsRead = TransferSizes(1, 32),
340    supportsWrite = TransferSizes(1, 32),
341    resources = uartDevice.reg
342  )
343  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
344    Seq(AXI4SlaveParameters(
345      address = peripheralRange,
346      regionType = RegionType.UNCACHED,
347      supportsRead = TransferSizes(1, 32),
348      supportsWrite = TransferSizes(1, 32),
349      interleavedId = Some(0)
350    ), uartParams),
351    beatBytes = 8
352  )))
353
354  val axi4peripheral_node = AXI4IdentityNode()
355  val error_xbar = Option.when(enableCHI)(TLXbar())
356
357  peripheralNode :=
358    AXI4UserYanker() :=
359    AXI4IdIndexer(idBits = 2) :=
360    AXI4Buffer() :=
361    AXI4Buffer() :=
362    AXI4Buffer() :=
363    AXI4Buffer() :=
364    AXI4UserYanker() :=
365    // AXI4Deinterleaver(8) :=
366    axi4peripheral_node
367
368  if (enableCHI) {
369    val error = LazyModule(new TLError(
370      params = DevNullParams(
371        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
372        maxAtomic = 8,
373        maxTransfer = 64),
374      beatBytes = 8
375    ))
376    error.node := error_xbar.get
377    axi4peripheral_node :=
378      AXI4Deinterleaver(8) :=
379      TLToAXI4() :=
380      error_xbar.get :=
381      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
382      TLFIFOFixer() :=
383      TLWidthWidget(L3OuterBusWidth / 8) :=
384      AXI4ToTL() :=
385      AXI4UserYanker() :=
386      soc_xbar.get
387  } else {
388    axi4peripheral_node :=
389      AXI4Deinterleaver(8) :=
390      TLToAXI4() :=
391      TLBuffer.chainNode(3) :=
392      peripheralXbar.get
393  }
394
395  val peripheral = InModuleBody {
396    peripheralNode.makeIOs()
397  }
398
399}
400
401class MemMisc()(implicit p: Parameters) extends BaseSoC
402  with HaveAXI4MemPort
403  with PMAConst
404  with HaveAXI4PeripheralPort
405{
406
407  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
408  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
409
410  val l3_in = TLTempNode()
411  val l3_out = TLTempNode()
412
413  val device_xbar = Option.when(enableCHI)(TLXbar())
414  device_xbar.foreach(_ := error_xbar.get)
415
416  if (l3_banked_xbar.isDefined) {
417    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
418    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
419  }
420  bankedNode match {
421    case Some(bankBinder) =>
422      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
423    case None =>
424  }
425
426  if(soc.L3CacheParamsOpt.isEmpty){
427    l3_out :*= l3_in
428  }
429
430  if (!enableCHI) {
431    for (port <- peripheral_ports.get) {
432      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
433    }
434  }
435
436  core_to_l3_ports.foreach { case _ =>
437    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
438      l3_banked_xbar.get :=*
439        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
440        TLBuffer() :=
441        core_out
442    }
443  }
444
445  val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8))
446  if (enableCHI) { clint.node := device_xbar.get }
447  else { clint.node := peripheralXbar.get }
448
449  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
450    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
451    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
452      val in = IO(Input(Vec(num, Bool())))
453      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
454    }
455    lazy val module = new IntSourceNodeToModuleImp(this)
456  }
457
458  val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8))
459  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
460
461  plic.intnode := plicSource.sourceNode
462  if (enableCHI) { plic.node := device_xbar.get }
463  else { plic.node := peripheralXbar.get }
464
465  val pll_node = TLRegisterNode(
466    address = Seq(soc.PLLRange),
467    device = new SimpleDevice("pll_ctrl", Seq()),
468    beatBytes = 8,
469    concurrency = 1
470  )
471  if (enableCHI) { pll_node := device_xbar.get }
472  else { pll_node := peripheralXbar.get }
473
474  val debugModule = LazyModule(new DebugModule(NumCores)(p))
475  val debugModuleXbarOpt = Option.when(SeperateDMBus)(TLXbar())
476  if (enableCHI) {
477    if (SeperateDMBus) {
478      debugModule.debug.node := debugModuleXbarOpt.get
479    } else {
480      debugModule.debug.node := device_xbar.get
481    }
482    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
483      error_xbar.get := sb2tl.node
484    }
485  } else {
486    if (SeperateDMBus) {
487      debugModule.debug.node := debugModuleXbarOpt.get
488    } else {
489      debugModule.debug.node := peripheralXbar.get
490    }
491    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
492      l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node
493    }
494  }
495
496  val pma = LazyModule(new TLPMA)
497  if (enableCHI) {
498    pma.node := TLBuffer.chainNode(4) := device_xbar.get
499    if (HasMEMencryption) {
500      axi4memencrpty.get.ctrl_node := TLToAPB() := device_xbar.get
501    }
502  } else {
503    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
504    if (HasMEMencryption) {
505      axi4memencrpty.get.ctrl_node := TLToAPB() := peripheralXbar.get
506    }
507  }
508
509  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
510
511    val debug_module_io = IO(new debugModule.DebugModuleIO)
512    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
513    val rtc_clock = IO(Input(Bool()))
514    val pll0_lock = IO(Input(Bool()))
515    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
516    val cacheable_check = IO(new TLPMAIO)
517    val clintTime = IO(Output(ValidIO(UInt(64.W))))
518
519    debugModule.module.io <> debug_module_io
520
521    // sync external interrupts
522    require(plicSource.module.in.length == ext_intrs.getWidth)
523    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
524      val ext_intr_sync = RegInit(0.U(3.W))
525      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
526      plic_in := ext_intr_sync(2)
527    }
528
529    pma.module.io <> cacheable_check
530
531    if (HasMEMencryption) {
532      val cnt = Counter(true.B, 8)._1
533      axi4memencrpty.get.module.io.random_val := axi4memencrpty.get.module.io.random_req && cnt(2).asBool
534      axi4memencrpty.get.module.io.random_data := cnt(0).asBool
535    }
536    // positive edge sampling of the lower-speed rtc_clock
537    val rtcTick = RegInit(0.U(3.W))
538    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
539    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
540
541    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
542    val pll_lock = RegNext(next = pll0_lock, init = false.B)
543
544    clintTime := clint.module.io.time
545
546    pll0_ctrl <> VecInit(pll_ctrl_regs)
547
548    pll_node.regmap(
549      0x000 -> RegFieldGroup(
550        "Pll", Some("PLL ctrl regs"),
551        pll_ctrl_regs.zipWithIndex.map{
552          case (r, i) => RegField(32, r, RegFieldDesc(
553            s"PLL_ctrl_$i",
554            desc = s"PLL ctrl register #$i"
555          ))
556        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
557          "PLL_lock",
558          "PLL lock register"
559        ))
560      )
561    )
562  }
563
564  lazy val module = new SoCMiscImp(this)
565}
566
567class SoCMisc()(implicit p: Parameters) extends MemMisc
568  with HaveSlaveAXI4Port
569
570