xref: /XiangShan/src/main/scala/system/SoC.scala (revision 25dc4a827ee27e3ccbaf02e8e5134872cba28fcd) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.tilelink._
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
28import freechips.rocketchip.tilelink._
29import huancun._
30import top.BusPerfMonitor
31import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
32import xiangshan.backend.fu.PMAConst
33import xiangshan.{DebugOptionsKey, XSTileKey}
34import coupledL2.EnableCHI
35
36case object SoCParamsKey extends Field[SoCParameters]
37
38case class SoCParameters
39(
40  EnableILA: Boolean = false,
41  PAddrBits: Int = 36,
42  extIntrs: Int = 64,
43  L3NBanks: Int = 4,
44  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
45    name = "L3",
46    level = 3,
47    ways = 8,
48    sets = 2048 // 1MB per bank
49  )),
50  XSTopPrefix: Option[String] = None,
51  NodeIDWidth: Int = 7,
52  NumHart: Int = 64,
53  NumIRFiles: Int = 7,
54  NumIRSrc: Int = 256,
55  UseXSNoCTop: Boolean = false,
56  IMSICUseTL: Boolean = false,
57){
58  // L3 configurations
59  val L3InnerBusWidth = 256
60  val L3BlockSize = 64
61  // on chip network configurations
62  val L3OuterBusWidth = 256
63}
64
65trait HasSoCParameter {
66  implicit val p: Parameters
67
68  val soc = p(SoCParamsKey)
69  val debugOpts = p(DebugOptionsKey)
70  val tiles = p(XSTileKey)
71  val enableCHI = p(EnableCHI)
72
73  val NumCores = tiles.size
74  val EnableILA = soc.EnableILA
75
76  // L3 configurations
77  val L3InnerBusWidth = soc.L3InnerBusWidth
78  val L3BlockSize = soc.L3BlockSize
79  val L3NBanks = soc.L3NBanks
80
81  // on chip network configurations
82  val L3OuterBusWidth = soc.L3OuterBusWidth
83
84  val NrExtIntr = soc.extIntrs
85
86  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
87
88  val NumIRSrc = soc.NumIRSrc
89}
90
91class ILABundle extends Bundle {}
92
93
94abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
95  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
96  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
97  val l3_xbar = Option.when(!enableCHI)(TLXbar())
98  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
99
100  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
101}
102
103// We adapt the following three traits from rocket-chip.
104// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
105trait HaveSlaveAXI4Port {
106  this: BaseSoC =>
107
108  val idBits = 14
109
110  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
111    Seq(AXI4MasterParameters(
112      name = "dma",
113      id = IdRange(0, 1 << idBits)
114    ))
115  )))
116
117  if (l3_xbar.isDefined) {
118    val errorDevice = LazyModule(new TLError(
119      params = DevNullParams(
120        address = Seq(AddressSet(0x0, 0x7fffffffL)),
121        maxAtomic = 8,
122        maxTransfer = 64),
123      beatBytes = L3InnerBusWidth / 8
124    ))
125    errorDevice.node :=
126      l3_xbar.get :=
127      TLFIFOFixer() :=
128      TLWidthWidget(32) :=
129      AXI4ToTL() :=
130      AXI4UserYanker(Some(1)) :=
131      AXI4Fragmenter() :=
132      AXI4Buffer() :=
133      AXI4Buffer() :=
134      AXI4IdIndexer(1) :=
135      l3FrontendAXI4Node
136  }
137
138  val dma = InModuleBody {
139    l3FrontendAXI4Node.makeIOs()
140  }
141}
142
143trait HaveAXI4MemPort {
144  this: BaseSoC =>
145  val device = new MemoryDevice
146  // 36-bit physical address
147  val memRange = AddressSet(0x00000000L, 0xfffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
148  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
149    AXI4SlavePortParameters(
150      slaves = Seq(
151        AXI4SlaveParameters(
152          address = memRange,
153          regionType = RegionType.UNCACHED,
154          executable = true,
155          supportsRead = TransferSizes(1, L3BlockSize),
156          supportsWrite = TransferSizes(1, L3BlockSize),
157          interleavedId = Some(0),
158          resources = device.reg("mem")
159        )
160      ),
161      beatBytes = L3OuterBusWidth / 8,
162      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
163    )
164  ))
165
166  val mem_xbar = TLXbar()
167  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
168  val axi4mem_node = AXI4IdentityNode()
169
170  if (enableCHI) {
171    axi4mem_node :=
172      soc_xbar.get
173  } else {
174    mem_xbar :=*
175      TLBuffer.chainNode(2) :=
176      TLCacheCork() :=
177      l3_mem_pmu :=
178      TLClientsMerger() :=
179      TLXbar() :=*
180      bankedNode.get
181
182    mem_xbar :=
183      TLWidthWidget(8) :=
184      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
185      peripheralXbar.get
186
187    axi4mem_node :=
188      TLToAXI4() :=
189      TLSourceShrinker(64) :=
190      TLWidthWidget(L3OuterBusWidth / 8) :=
191      TLBuffer.chainNode(2) :=
192      mem_xbar
193  }
194
195  memAXI4SlaveNode :=
196    AXI4Buffer() :=
197    AXI4Buffer() :=
198    AXI4Buffer() :=
199    AXI4IdIndexer(idBits = 14) :=
200    AXI4UserYanker() :=
201    AXI4Deinterleaver(L3BlockSize) :=
202    axi4mem_node
203
204  val memory = InModuleBody {
205    memAXI4SlaveNode.makeIOs()
206  }
207}
208
209trait HaveAXI4PeripheralPort { this: BaseSoC =>
210  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
211  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
212  val uartRange = AddressSet(0x40600000, 0x3f)
213  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
214  val uartParams = AXI4SlaveParameters(
215    address = Seq(uartRange),
216    regionType = RegionType.UNCACHED,
217    supportsRead = TransferSizes(1, 32),
218    supportsWrite = TransferSizes(1, 32),
219    resources = uartDevice.reg
220  )
221  val peripheralRange = AddressSet(
222    0x0, 0x7fffffff
223  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
224  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
225    Seq(AXI4SlaveParameters(
226      address = peripheralRange,
227      regionType = RegionType.UNCACHED,
228      supportsRead = TransferSizes(1, 32),
229      supportsWrite = TransferSizes(1, 32),
230      interleavedId = Some(0)
231    ), uartParams),
232    beatBytes = 8
233  )))
234
235  val axi4peripheral_node = AXI4IdentityNode()
236  val error_xbar = Option.when(enableCHI)(TLXbar())
237
238  peripheralNode :=
239    AXI4UserYanker() :=
240    AXI4IdIndexer(idBits = 2) :=
241    AXI4Buffer() :=
242    AXI4Buffer() :=
243    AXI4Buffer() :=
244    AXI4Buffer() :=
245    AXI4UserYanker() :=
246    // AXI4Deinterleaver(8) :=
247    axi4peripheral_node
248
249  if (enableCHI) {
250    val error = LazyModule(new TLError(
251      params = DevNullParams(
252        address = Seq(AddressSet(0x1000000000L, 0xfffffffffL)),
253        maxAtomic = 8,
254        maxTransfer = 64),
255      beatBytes = 8
256    ))
257    error.node := error_xbar.get
258    axi4peripheral_node :=
259      AXI4Deinterleaver(8) :=
260      TLToAXI4() :=
261      error_xbar.get :=
262      TLFIFOFixer() :=
263      TLWidthWidget(L3OuterBusWidth / 8) :=
264      AXI4ToTL() :=
265      AXI4UserYanker() :=
266      soc_xbar.get
267  } else {
268    axi4peripheral_node :=
269      AXI4Deinterleaver(8) :=
270      TLToAXI4() :=
271      TLBuffer.chainNode(3) :=
272      peripheralXbar.get
273  }
274
275  val peripheral = InModuleBody {
276    peripheralNode.makeIOs()
277  }
278
279}
280
281class MemMisc()(implicit p: Parameters) extends BaseSoC
282  with HaveAXI4MemPort
283  with PMAConst
284  with HaveAXI4PeripheralPort
285{
286
287  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
288  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
289
290  val l3_in = TLTempNode()
291  val l3_out = TLTempNode()
292
293  val device_xbar = Option.when(enableCHI)(TLXbar())
294  device_xbar.foreach(_ := error_xbar.get)
295
296  if (l3_banked_xbar.isDefined) {
297    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
298    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
299  }
300  bankedNode match {
301    case Some(bankBinder) =>
302      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
303    case None =>
304  }
305
306  if(soc.L3CacheParamsOpt.isEmpty){
307    l3_out :*= l3_in
308  }
309
310  if (!enableCHI) {
311    for (port <- peripheral_ports.get) {
312      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
313    }
314  }
315
316  core_to_l3_ports.foreach { case _ =>
317    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
318      l3_banked_xbar.get :=*
319        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
320        TLBuffer() :=
321        core_out
322    }
323  }
324
325  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
326  if (enableCHI) { clint.node := device_xbar.get }
327  else { clint.node := peripheralXbar.get }
328
329  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
330    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
331    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
332      val in = IO(Input(Vec(num, Bool())))
333      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
334    }
335    lazy val module = new IntSourceNodeToModuleImp(this)
336  }
337
338  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
339  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
340
341  plic.intnode := plicSource.sourceNode
342  if (enableCHI) { plic.node := device_xbar.get }
343  else { plic.node := peripheralXbar.get }
344
345  val pll_node = TLRegisterNode(
346    address = Seq(AddressSet(0x3a000000L, 0xfff)),
347    device = new SimpleDevice("pll_ctrl", Seq()),
348    beatBytes = 8,
349    concurrency = 1
350  )
351  if (enableCHI) { pll_node := device_xbar.get }
352  else { pll_node := peripheralXbar.get }
353
354  val debugModule = LazyModule(new DebugModule(NumCores)(p))
355  if (enableCHI) {
356    debugModule.debug.node := device_xbar.get
357    // TODO: l3_xbar
358    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
359      error_xbar.get := sb2tl.node
360    }
361  } else {
362    debugModule.debug.node := peripheralXbar.get
363    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
364      l3_xbar.get := TLBuffer() := sb2tl.node
365    }
366  }
367
368  val pma = LazyModule(new TLPMA)
369  if (enableCHI) {
370    pma.node := TLBuffer.chainNode(4) := device_xbar.get
371  } else {
372    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
373  }
374
375  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
376
377    val debug_module_io = IO(new debugModule.DebugModuleIO)
378    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
379    val rtc_clock = IO(Input(Bool()))
380    val pll0_lock = IO(Input(Bool()))
381    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
382    val cacheable_check = IO(new TLPMAIO)
383
384    debugModule.module.io <> debug_module_io
385
386    // sync external interrupts
387    require(plicSource.module.in.length == ext_intrs.getWidth)
388    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
389      val ext_intr_sync = RegInit(0.U(3.W))
390      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
391      plic_in := ext_intr_sync(2)
392    }
393
394    pma.module.io <> cacheable_check
395
396    // positive edge sampling of the lower-speed rtc_clock
397    val rtcTick = RegInit(0.U(3.W))
398    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
399    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
400
401    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
402    val pll_lock = RegNext(next = pll0_lock, init = false.B)
403
404    pll0_ctrl <> VecInit(pll_ctrl_regs)
405
406    pll_node.regmap(
407      0x000 -> RegFieldGroup(
408        "Pll", Some("PLL ctrl regs"),
409        pll_ctrl_regs.zipWithIndex.map{
410          case (r, i) => RegField(32, r, RegFieldDesc(
411            s"PLL_ctrl_$i",
412            desc = s"PLL ctrl register #$i"
413          ))
414        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
415          "PLL_lock",
416          "PLL lock register"
417        ))
418      )
419    )
420  }
421
422  lazy val module = new SoCMiscImp(this)
423}
424
425class SoCMisc()(implicit p: Parameters) extends MemMisc
426  with HaveSlaveAXI4Port
427
428