xref: /XiangShan/src/main/scala/system/SoC.scala (revision 222e17e50aa21acebeceb8af532f5dd71b048eda) 
1package system
2
3import chipsalliance.rocketchip.config.Parameters
4import device.{AXI4Timer, TLTimer}
5import chisel3._
6import chisel3.util._
7import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
8import freechips.rocketchip.tilelink.{TLFuzzer, TLIdentityNode, TLXbar}
9import xiangshan.{HasXSParameter, XSCore}
10
11
12case class SoCParameters
13(
14  EnableILA: Boolean = false,
15  HasL2Cache: Boolean = false,
16  HasPrefetch: Boolean = false
17)
18
19trait HasSoCParameter extends HasXSParameter{
20  val soc = top.Parameters.get.socParameters
21  val EnableILA = soc.EnableILA
22  val HasL2cache = soc.HasL2Cache
23  val HasPrefetch = soc.HasPrefetch
24}
25
26class ILABundle extends Bundle {}
27
28
29class DummyCore()(implicit p: Parameters) extends LazyModule {
30  val mem = TLFuzzer(nOperations = 10)
31  val mmio = TLFuzzer(nOperations = 10)
32
33  lazy val module = new LazyModuleImp(this){
34
35  }
36}
37
38
39class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
40
41  private val xsCore = LazyModule(new XSCore())
42
43  // only mem and extDev visible externally
44  val mem = xsCore.mem
45  val extDev = TLIdentityNode()
46
47  private val mmioXbar = TLXbar()
48  private val clint = LazyModule(new TLTimer(
49    Seq(AddressSet(0x38000000L, 0x0000ffffL)),
50    sim = !env.FPGAPlatform
51  ))
52
53  mmioXbar := xsCore.mmio
54  clint.node := mmioXbar
55  extDev := mmioXbar
56
57  lazy val module = new LazyModuleImp(this){
58    val io = IO(new Bundle{
59      val meip = Input(Bool())
60      val ila = if(env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
61    })
62    val mtipSync = WireInit(0.U(1.W)) //clint.module.mtip
63    val meipSync = RegNext(RegNext(io.meip))
64    ExcitingUtils.addSource(mtipSync, "mtip")
65    ExcitingUtils.addSource(meipSync, "meip")
66  }
67
68}
69
70
71//class XSSoc extends Module with HasSoCParameter {
72//  val io = IO(new Bundle{
73//    val mem = new TLCached(l1BusParams)
74//    val mmio = new TLCached(l1BusParams)
75//    val frontend = Flipped(new AXI4) //TODO: do we need it ?
76//    val meip = Input(Bool())
77//    val ila = if (env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
78//  })
79//
80//  val xsCore = Module(new XSCore)
81//
82//  io.frontend <> DontCare
83//
84//  io.mem <> xsCore.io.mem
85//
86//  val addrSpace = List(
87//    (0x40000000L, 0x40000000L), // external devices
88//    (0x38000000L, 0x00010000L)  // CLINT
89//  )
90//  val mmioXbar = Module(new NaiveTL1toN(addrSpace, xsCore.io.mem.params))
91//  mmioXbar.io.in <> xsCore.io.mmio
92//
93//  val extDev = mmioXbar.io.out(0)
94//  val clint = Module(new AXI4Timer(sim = !env.FPGAPlatform))
95//  clint.io.in <> AXI4ToAXI4Lite(MMIOTLToAXI4(mmioXbar.io.out(1)))
96//
97//  io.mmio <> extDev
98//
99//  val mtipSync = clint.io.extra.get.mtip
100//  val meipSync = RegNext(RegNext(io.meip))
101//  ExcitingUtils.addSource(mtipSync, "mtip")
102//  ExcitingUtils.addSource(meipSync, "meip")
103//}
104