xref: /XiangShan/src/main/scala/system/SoC.scala (revision 211d620b07edb797ba35b635d24fef4e7294bae2) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.debug.DebugModuleKey
25import freechips.rocketchip.devices.tilelink._
26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.PMAConst
35import xiangshan.{DebugOptionsKey, XSTileKey}
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
39import xiangshan.PMParameKey
40
41case object SoCParamsKey extends Field[SoCParameters]
42
43case class SoCParameters
44(
45  EnableILA: Boolean = false,
46  PAddrBits: Int = 48,
47  PmemRanges: Seq[(BigInt, BigInt)] = Seq((0x80000000L, 0x80000000000L)),
48  CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
49  BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
50  PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
51  PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
52  UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
53  extIntrs: Int = 64,
54  L3NBanks: Int = 4,
55  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
56    name = "L3",
57    level = 3,
58    ways = 8,
59    sets = 2048 // 1MB per bank
60  )),
61  OpenLLCParamsOpt: Option[OpenLLCParam] = Some(OpenLLCParam(
62    name = "LLC",
63    ways = 8,
64    sets = 2048,
65    banks = 4,
66    clientCaches = Seq(L2Param())
67  )),
68  XSTopPrefix: Option[String] = None,
69  NodeIDWidthList: Map[String, Int] = Map(
70    "B" -> 7,
71    "E.b" -> 11
72  ),
73  NumHart: Int = 64,
74  NumIRFiles: Int = 7,
75  NumIRSrc: Int = 256,
76  UseXSNoCTop: Boolean = false,
77  IMSICUseTL: Boolean = false,
78  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
79  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
80){
81  // L3 configurations
82  val L3InnerBusWidth = 256
83  val L3BlockSize = 64
84  // on chip network configurations
85  val L3OuterBusWidth = 256
86  val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf)
87}
88
89trait HasSoCParameter {
90  implicit val p: Parameters
91
92  val soc = p(SoCParamsKey)
93  val debugOpts = p(DebugOptionsKey)
94  val tiles = p(XSTileKey)
95  val enableCHI = p(EnableCHI)
96  val issue = p(CHIIssue)
97
98  val NumCores = tiles.size
99  val EnableILA = soc.EnableILA
100
101  // L3 configurations
102  val L3InnerBusWidth = soc.L3InnerBusWidth
103  val L3BlockSize = soc.L3BlockSize
104  val L3NBanks = soc.L3NBanks
105
106  // on chip network configurations
107  val L3OuterBusWidth = soc.L3OuterBusWidth
108
109  val NrExtIntr = soc.extIntrs
110
111  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
112
113  val NumIRSrc = soc.NumIRSrc
114
115  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
116    soc.EnableCHIAsyncBridge else None
117  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
118}
119
120trait HasPeripheralRanges {
121  implicit val p: Parameters
122
123  private def soc = p(SoCParamsKey)
124  private def dm = p(DebugModuleKey)
125  private def pmParams = p(PMParameKey)
126
127  private def mmpma = pmParams.mmpma
128
129  def onChipPeripheralRanges: Map[String, AddressSet] = Map(
130    "CLINT" -> soc.CLINTRange,
131    "BEU"   -> soc.BEURange,
132    "PLIC"  -> soc.PLICRange,
133    "PLL"   -> soc.PLLRange,
134    "UART"  -> soc.UARTLiteRange,
135    "DEBUG" -> dm.get.address,
136    "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
137  ) ++ (
138    if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false))
139      Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff))
140    else
141      Map()
142  )
143
144  def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) =>
145    acc.flatMap(_.subtract(x))
146  }
147}
148
149class ILABundle extends Bundle {}
150
151
152abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges {
153  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
154  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
155  val l3_xbar = Option.when(!enableCHI)(TLXbar())
156  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
157
158  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
159}
160
161// We adapt the following three traits from rocket-chip.
162// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
163trait HaveSlaveAXI4Port {
164  this: BaseSoC =>
165
166  val idBits = 14
167
168  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
169    Seq(AXI4MasterParameters(
170      name = "dma",
171      id = IdRange(0, 1 << idBits)
172    ))
173  )))
174
175  if (l3_xbar.isDefined) {
176    val errorDevice = LazyModule(new TLError(
177      params = DevNullParams(
178        address = Seq(AddressSet(0x0, 0x7fffffffL)),
179        maxAtomic = 8,
180        maxTransfer = 64),
181      beatBytes = L3InnerBusWidth / 8
182    ))
183    errorDevice.node :=
184      l3_xbar.get :=
185      TLFIFOFixer() :=
186      TLWidthWidget(32) :=
187      AXI4ToTL() :=
188      AXI4UserYanker(Some(1)) :=
189      AXI4Fragmenter() :=
190      AXI4Buffer() :=
191      AXI4Buffer() :=
192      AXI4IdIndexer(1) :=
193      l3FrontendAXI4Node
194  }
195
196  val dma = InModuleBody {
197    l3FrontendAXI4Node.makeIOs()
198  }
199}
200
201trait HaveAXI4MemPort {
202  this: BaseSoC =>
203  val device = new MemoryDevice
204  // 48-bit physical address
205  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
206  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
207    AXI4SlavePortParameters(
208      slaves = Seq(
209        AXI4SlaveParameters(
210          address = memRange,
211          regionType = RegionType.UNCACHED,
212          executable = true,
213          supportsRead = TransferSizes(1, L3BlockSize),
214          supportsWrite = TransferSizes(1, L3BlockSize),
215          interleavedId = Some(0),
216          resources = device.reg("mem")
217        )
218      ),
219      beatBytes = L3OuterBusWidth / 8,
220      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
221    )
222  ))
223
224  val mem_xbar = TLXbar()
225  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
226  val axi4mem_node = AXI4IdentityNode()
227
228  if (enableCHI) {
229    axi4mem_node :=
230      soc_xbar.get
231  } else {
232    mem_xbar :=*
233      TLBuffer.chainNode(2) :=
234      TLCacheCork() :=
235      l3_mem_pmu :=
236      TLClientsMerger() :=
237      TLXbar() :=*
238      bankedNode.get
239
240    mem_xbar :=
241      TLWidthWidget(8) :=
242      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
243      peripheralXbar.get
244
245    axi4mem_node :=
246      TLToAXI4() :=
247      TLSourceShrinker(64) :=
248      TLWidthWidget(L3OuterBusWidth / 8) :=
249      TLBuffer.chainNode(2) :=
250      mem_xbar
251  }
252
253  memAXI4SlaveNode :=
254    AXI4Buffer() :=
255    AXI4Buffer() :=
256    AXI4Buffer() :=
257    AXI4IdIndexer(idBits = 14) :=
258    AXI4UserYanker() :=
259    AXI4Deinterleaver(L3BlockSize) :=
260    axi4mem_node
261
262  val memory = InModuleBody {
263    memAXI4SlaveNode.makeIOs()
264  }
265}
266
267trait HaveAXI4PeripheralPort { this: BaseSoC =>
268  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
269  val uartParams = AXI4SlaveParameters(
270    address = Seq(soc.UARTLiteRange),
271    regionType = RegionType.UNCACHED,
272    supportsRead = TransferSizes(1, 32),
273    supportsWrite = TransferSizes(1, 32),
274    resources = uartDevice.reg
275  )
276  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
277    Seq(AXI4SlaveParameters(
278      address = peripheralRange,
279      regionType = RegionType.UNCACHED,
280      supportsRead = TransferSizes(1, 32),
281      supportsWrite = TransferSizes(1, 32),
282      interleavedId = Some(0)
283    ), uartParams),
284    beatBytes = 8
285  )))
286
287  val axi4peripheral_node = AXI4IdentityNode()
288  val error_xbar = Option.when(enableCHI)(TLXbar())
289
290  peripheralNode :=
291    AXI4UserYanker() :=
292    AXI4IdIndexer(idBits = 2) :=
293    AXI4Buffer() :=
294    AXI4Buffer() :=
295    AXI4Buffer() :=
296    AXI4Buffer() :=
297    AXI4UserYanker() :=
298    // AXI4Deinterleaver(8) :=
299    axi4peripheral_node
300
301  if (enableCHI) {
302    val error = LazyModule(new TLError(
303      params = DevNullParams(
304        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
305        maxAtomic = 8,
306        maxTransfer = 64),
307      beatBytes = 8
308    ))
309    error.node := error_xbar.get
310    axi4peripheral_node :=
311      AXI4Deinterleaver(8) :=
312      TLToAXI4() :=
313      error_xbar.get :=
314      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
315      TLFIFOFixer() :=
316      TLWidthWidget(L3OuterBusWidth / 8) :=
317      AXI4ToTL() :=
318      AXI4UserYanker() :=
319      soc_xbar.get
320  } else {
321    axi4peripheral_node :=
322      AXI4Deinterleaver(8) :=
323      TLToAXI4() :=
324      TLBuffer.chainNode(3) :=
325      peripheralXbar.get
326  }
327
328  val peripheral = InModuleBody {
329    peripheralNode.makeIOs()
330  }
331
332}
333
334class MemMisc()(implicit p: Parameters) extends BaseSoC
335  with HaveAXI4MemPort
336  with PMAConst
337  with HaveAXI4PeripheralPort
338{
339
340  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
341  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
342
343  val l3_in = TLTempNode()
344  val l3_out = TLTempNode()
345
346  val device_xbar = Option.when(enableCHI)(TLXbar())
347  device_xbar.foreach(_ := error_xbar.get)
348
349  if (l3_banked_xbar.isDefined) {
350    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
351    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
352  }
353  bankedNode match {
354    case Some(bankBinder) =>
355      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
356    case None =>
357  }
358
359  if(soc.L3CacheParamsOpt.isEmpty){
360    l3_out :*= l3_in
361  }
362
363  if (!enableCHI) {
364    for (port <- peripheral_ports.get) {
365      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
366    }
367  }
368
369  core_to_l3_ports.foreach { case _ =>
370    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
371      l3_banked_xbar.get :=*
372        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
373        TLBuffer() :=
374        core_out
375    }
376  }
377
378  val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8))
379  if (enableCHI) { clint.node := device_xbar.get }
380  else { clint.node := peripheralXbar.get }
381
382  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
383    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
384    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
385      val in = IO(Input(Vec(num, Bool())))
386      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
387    }
388    lazy val module = new IntSourceNodeToModuleImp(this)
389  }
390
391  val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8))
392  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
393
394  plic.intnode := plicSource.sourceNode
395  if (enableCHI) { plic.node := device_xbar.get }
396  else { plic.node := peripheralXbar.get }
397
398  val pll_node = TLRegisterNode(
399    address = Seq(soc.PLLRange),
400    device = new SimpleDevice("pll_ctrl", Seq()),
401    beatBytes = 8,
402    concurrency = 1
403  )
404  if (enableCHI) { pll_node := device_xbar.get }
405  else { pll_node := peripheralXbar.get }
406
407  val debugModule = LazyModule(new DebugModule(NumCores)(p))
408  if (enableCHI) {
409    debugModule.debug.node := device_xbar.get
410    // TODO: l3_xbar
411    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
412      error_xbar.get := sb2tl.node
413    }
414  } else {
415    debugModule.debug.node := peripheralXbar.get
416    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
417      l3_xbar.get := TLBuffer() := sb2tl.node
418    }
419  }
420
421  val pma = LazyModule(new TLPMA)
422  if (enableCHI) {
423    pma.node := TLBuffer.chainNode(4) := device_xbar.get
424  } else {
425    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
426  }
427
428  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
429
430    val debug_module_io = IO(new debugModule.DebugModuleIO)
431    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
432    val rtc_clock = IO(Input(Bool()))
433    val pll0_lock = IO(Input(Bool()))
434    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
435    val cacheable_check = IO(new TLPMAIO)
436    val clintTime = IO(Output(ValidIO(UInt(64.W))))
437
438    debugModule.module.io <> debug_module_io
439
440    // sync external interrupts
441    require(plicSource.module.in.length == ext_intrs.getWidth)
442    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
443      val ext_intr_sync = RegInit(0.U(3.W))
444      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
445      plic_in := ext_intr_sync(2)
446    }
447
448    pma.module.io <> cacheable_check
449
450    // positive edge sampling of the lower-speed rtc_clock
451    val rtcTick = RegInit(0.U(3.W))
452    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
453    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
454
455    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
456    val pll_lock = RegNext(next = pll0_lock, init = false.B)
457
458    clintTime := clint.module.io.time
459
460    pll0_ctrl <> VecInit(pll_ctrl_regs)
461
462    pll_node.regmap(
463      0x000 -> RegFieldGroup(
464        "Pll", Some("PLL ctrl regs"),
465        pll_ctrl_regs.zipWithIndex.map{
466          case (r, i) => RegField(32, r, RegFieldDesc(
467            s"PLL_ctrl_$i",
468            desc = s"PLL ctrl register #$i"
469          ))
470        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
471          "PLL_lock",
472          "PLL lock register"
473        ))
474      )
475    )
476  }
477
478  lazy val module = new SoCMiscImp(this)
479}
480
481class SoCMisc()(implicit p: Parameters) extends MemMisc
482  with HaveSlaveAXI4Port
483
484