xref: /XiangShan/src/main/scala/system/SoC.scala (revision 1bc48dd1fa0af361fd194c65bad3b86349ec2903) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.tilelink._
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
28import freechips.rocketchip.tilelink._
29import freechips.rocketchip.util.AsyncQueueParams
30import huancun._
31import top.BusPerfMonitor
32import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
33import xiangshan.backend.fu.PMAConst
34import xiangshan.{DebugOptionsKey, XSTileKey}
35import coupledL2.EnableCHI
36import coupledL2.tl2chi.CHIIssue
37
38case object SoCParamsKey extends Field[SoCParameters]
39
40case class SoCParameters
41(
42  EnableILA: Boolean = false,
43  PAddrBits: Int = 48,
44  PmemRanges: Seq[(BigInt, BigInt)] = Seq((0x80000000L, 0x80000000000L)),
45  extIntrs: Int = 64,
46  L3NBanks: Int = 4,
47  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
48    name = "L3",
49    level = 3,
50    ways = 8,
51    sets = 2048 // 1MB per bank
52  )),
53  XSTopPrefix: Option[String] = None,
54  NodeIDWidthList: Map[String, Int] = Map(
55    "B" -> 7,
56    "E.b" -> 11
57  ),
58  NumHart: Int = 64,
59  NumIRFiles: Int = 7,
60  NumIRSrc: Int = 256,
61  UseXSNoCTop: Boolean = false,
62  IMSICUseTL: Boolean = false,
63  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 4, sync = 3, safe = false)),
64  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
65){
66  // L3 configurations
67  val L3InnerBusWidth = 256
68  val L3BlockSize = 64
69  // on chip network configurations
70  val L3OuterBusWidth = 256
71}
72
73trait HasSoCParameter {
74  implicit val p: Parameters
75
76  val soc = p(SoCParamsKey)
77  val debugOpts = p(DebugOptionsKey)
78  val tiles = p(XSTileKey)
79  val enableCHI = p(EnableCHI)
80  val issue = p(CHIIssue)
81
82  val NumCores = tiles.size
83  val EnableILA = soc.EnableILA
84
85  // L3 configurations
86  val L3InnerBusWidth = soc.L3InnerBusWidth
87  val L3BlockSize = soc.L3BlockSize
88  val L3NBanks = soc.L3NBanks
89
90  // on chip network configurations
91  val L3OuterBusWidth = soc.L3OuterBusWidth
92
93  val NrExtIntr = soc.extIntrs
94
95  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
96
97  val NumIRSrc = soc.NumIRSrc
98
99  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
100    soc.EnableCHIAsyncBridge else None
101  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
102}
103
104class ILABundle extends Bundle {}
105
106
107abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
108  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
109  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
110  val l3_xbar = Option.when(!enableCHI)(TLXbar())
111  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
112
113  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
114}
115
116// We adapt the following three traits from rocket-chip.
117// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
118trait HaveSlaveAXI4Port {
119  this: BaseSoC =>
120
121  val idBits = 14
122
123  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
124    Seq(AXI4MasterParameters(
125      name = "dma",
126      id = IdRange(0, 1 << idBits)
127    ))
128  )))
129
130  if (l3_xbar.isDefined) {
131    val errorDevice = LazyModule(new TLError(
132      params = DevNullParams(
133        address = Seq(AddressSet(0x0, 0x7fffffffL)),
134        maxAtomic = 8,
135        maxTransfer = 64),
136      beatBytes = L3InnerBusWidth / 8
137    ))
138    errorDevice.node :=
139      l3_xbar.get :=
140      TLFIFOFixer() :=
141      TLWidthWidget(32) :=
142      AXI4ToTL() :=
143      AXI4UserYanker(Some(1)) :=
144      AXI4Fragmenter() :=
145      AXI4Buffer() :=
146      AXI4Buffer() :=
147      AXI4IdIndexer(1) :=
148      l3FrontendAXI4Node
149  }
150
151  val dma = InModuleBody {
152    l3FrontendAXI4Node.makeIOs()
153  }
154}
155
156trait HaveAXI4MemPort {
157  this: BaseSoC =>
158  val device = new MemoryDevice
159  // 48-bit physical address
160  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
161  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
162    AXI4SlavePortParameters(
163      slaves = Seq(
164        AXI4SlaveParameters(
165          address = memRange,
166          regionType = RegionType.UNCACHED,
167          executable = true,
168          supportsRead = TransferSizes(1, L3BlockSize),
169          supportsWrite = TransferSizes(1, L3BlockSize),
170          interleavedId = Some(0),
171          resources = device.reg("mem")
172        )
173      ),
174      beatBytes = L3OuterBusWidth / 8,
175      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
176    )
177  ))
178
179  val mem_xbar = TLXbar()
180  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
181  val axi4mem_node = AXI4IdentityNode()
182
183  if (enableCHI) {
184    axi4mem_node :=
185      soc_xbar.get
186  } else {
187    mem_xbar :=*
188      TLBuffer.chainNode(2) :=
189      TLCacheCork() :=
190      l3_mem_pmu :=
191      TLClientsMerger() :=
192      TLXbar() :=*
193      bankedNode.get
194
195    mem_xbar :=
196      TLWidthWidget(8) :=
197      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
198      peripheralXbar.get
199
200    axi4mem_node :=
201      TLToAXI4() :=
202      TLSourceShrinker(64) :=
203      TLWidthWidget(L3OuterBusWidth / 8) :=
204      TLBuffer.chainNode(2) :=
205      mem_xbar
206  }
207
208  memAXI4SlaveNode :=
209    AXI4Buffer() :=
210    AXI4Buffer() :=
211    AXI4Buffer() :=
212    AXI4IdIndexer(idBits = 14) :=
213    AXI4UserYanker() :=
214    AXI4Deinterleaver(L3BlockSize) :=
215    axi4mem_node
216
217  val memory = InModuleBody {
218    memAXI4SlaveNode.makeIOs()
219  }
220}
221
222trait HaveAXI4PeripheralPort { this: BaseSoC =>
223  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
224  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
225  val uartRange = AddressSet(0x40600000, 0x3f)
226  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
227  val uartParams = AXI4SlaveParameters(
228    address = Seq(uartRange),
229    regionType = RegionType.UNCACHED,
230    supportsRead = TransferSizes(1, 32),
231    supportsWrite = TransferSizes(1, 32),
232    resources = uartDevice.reg
233  )
234  val peripheralRange = AddressSet(
235    0x0, 0x7fffffff
236  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
237  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
238    Seq(AXI4SlaveParameters(
239      address = peripheralRange,
240      regionType = RegionType.UNCACHED,
241      supportsRead = TransferSizes(1, 32),
242      supportsWrite = TransferSizes(1, 32),
243      interleavedId = Some(0)
244    ), uartParams),
245    beatBytes = 8
246  )))
247
248  val axi4peripheral_node = AXI4IdentityNode()
249  val error_xbar = Option.when(enableCHI)(TLXbar())
250
251  peripheralNode :=
252    AXI4UserYanker() :=
253    AXI4IdIndexer(idBits = 2) :=
254    AXI4Buffer() :=
255    AXI4Buffer() :=
256    AXI4Buffer() :=
257    AXI4Buffer() :=
258    AXI4UserYanker() :=
259    // AXI4Deinterleaver(8) :=
260    axi4peripheral_node
261
262  if (enableCHI) {
263    val error = LazyModule(new TLError(
264      params = DevNullParams(
265        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
266        maxAtomic = 8,
267        maxTransfer = 64),
268      beatBytes = 8
269    ))
270    error.node := error_xbar.get
271    axi4peripheral_node :=
272      AXI4Deinterleaver(8) :=
273      TLToAXI4() :=
274      error_xbar.get :=
275      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
276      TLFIFOFixer() :=
277      TLWidthWidget(L3OuterBusWidth / 8) :=
278      AXI4ToTL() :=
279      AXI4UserYanker() :=
280      soc_xbar.get
281  } else {
282    axi4peripheral_node :=
283      AXI4Deinterleaver(8) :=
284      TLToAXI4() :=
285      TLBuffer.chainNode(3) :=
286      peripheralXbar.get
287  }
288
289  val peripheral = InModuleBody {
290    peripheralNode.makeIOs()
291  }
292
293}
294
295class MemMisc()(implicit p: Parameters) extends BaseSoC
296  with HaveAXI4MemPort
297  with PMAConst
298  with HaveAXI4PeripheralPort
299{
300
301  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
302  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
303
304  val l3_in = TLTempNode()
305  val l3_out = TLTempNode()
306
307  val device_xbar = Option.when(enableCHI)(TLXbar())
308  device_xbar.foreach(_ := error_xbar.get)
309
310  if (l3_banked_xbar.isDefined) {
311    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
312    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
313  }
314  bankedNode match {
315    case Some(bankBinder) =>
316      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
317    case None =>
318  }
319
320  if(soc.L3CacheParamsOpt.isEmpty){
321    l3_out :*= l3_in
322  }
323
324  if (!enableCHI) {
325    for (port <- peripheral_ports.get) {
326      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
327    }
328  }
329
330  core_to_l3_ports.foreach { case _ =>
331    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
332      l3_banked_xbar.get :=*
333        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
334        TLBuffer() :=
335        core_out
336    }
337  }
338
339  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
340  if (enableCHI) { clint.node := device_xbar.get }
341  else { clint.node := peripheralXbar.get }
342
343  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
344    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
345    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
346      val in = IO(Input(Vec(num, Bool())))
347      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
348    }
349    lazy val module = new IntSourceNodeToModuleImp(this)
350  }
351
352  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
353  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
354
355  plic.intnode := plicSource.sourceNode
356  if (enableCHI) { plic.node := device_xbar.get }
357  else { plic.node := peripheralXbar.get }
358
359  val pll_node = TLRegisterNode(
360    address = Seq(AddressSet(0x3a000000L, 0xfff)),
361    device = new SimpleDevice("pll_ctrl", Seq()),
362    beatBytes = 8,
363    concurrency = 1
364  )
365  if (enableCHI) { pll_node := device_xbar.get }
366  else { pll_node := peripheralXbar.get }
367
368  val debugModule = LazyModule(new DebugModule(NumCores)(p))
369  if (enableCHI) {
370    debugModule.debug.node := device_xbar.get
371    // TODO: l3_xbar
372    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
373      error_xbar.get := sb2tl.node
374    }
375  } else {
376    debugModule.debug.node := peripheralXbar.get
377    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
378      l3_xbar.get := TLBuffer() := sb2tl.node
379    }
380  }
381
382  val pma = LazyModule(new TLPMA)
383  if (enableCHI) {
384    pma.node := TLBuffer.chainNode(4) := device_xbar.get
385  } else {
386    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
387  }
388
389  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
390
391    val debug_module_io = IO(new debugModule.DebugModuleIO)
392    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
393    val rtc_clock = IO(Input(Bool()))
394    val pll0_lock = IO(Input(Bool()))
395    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
396    val cacheable_check = IO(new TLPMAIO)
397    val clintTime = IO(Output(ValidIO(UInt(64.W))))
398
399    debugModule.module.io <> debug_module_io
400
401    // sync external interrupts
402    require(plicSource.module.in.length == ext_intrs.getWidth)
403    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
404      val ext_intr_sync = RegInit(0.U(3.W))
405      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
406      plic_in := ext_intr_sync(2)
407    }
408
409    pma.module.io <> cacheable_check
410
411    // positive edge sampling of the lower-speed rtc_clock
412    val rtcTick = RegInit(0.U(3.W))
413    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
414    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
415
416    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
417    val pll_lock = RegNext(next = pll0_lock, init = false.B)
418
419    clintTime := clint.module.io.time
420
421    pll0_ctrl <> VecInit(pll_ctrl_regs)
422
423    pll_node.regmap(
424      0x000 -> RegFieldGroup(
425        "Pll", Some("PLL ctrl regs"),
426        pll_ctrl_regs.zipWithIndex.map{
427          case (r, i) => RegField(32, r, RegFieldDesc(
428            s"PLL_ctrl_$i",
429            desc = s"PLL ctrl register #$i"
430          ))
431        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
432          "PLL_lock",
433          "PLL lock register"
434        ))
435      )
436    )
437  }
438
439  lazy val module = new SoCMiscImp(this)
440}
441
442class SoCMisc()(implicit p: Parameters) extends MemMisc
443  with HaveSlaveAXI4Port
444
445