xref: /XiangShan/src/main/scala/system/SoC.scala (revision 1b2d260fdeb9d070d78b019d381c2b1550e70cf5) 
1package system
2
3import noop._
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6import device.AXI4Timer
7
8import chisel3._
9import chisel3.util._
10import chisel3.util.experimental.BoringUtils
11
12trait HasSoCParameter {
13  val EnableILA = false
14  val HasL2cache = true
15  val HasPrefetch = true
16}
17
18class ILABundle extends Bundle {
19  val WBUpc = UInt(32.W)
20  val WBUvalid = UInt(1.W)
21  val WBUrfWen = UInt(1.W)
22  val WBUrfDest = UInt(5.W)
23  val WBUrfData = UInt(64.W)
24  val InstrCnt = UInt(64.W)
25}
26
27class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
28  val io = IO(new Bundle{
29    val mem = new AXI4
30    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
31    val frontend = Flipped(new AXI4)
32    val mtip = Input(Bool())
33    val meip = Input(Bool())
34    val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
35  })
36
37  val noop = Module(new NOOP)
38  val cohMg = Module(new CoherenceManager)
39  val xbar = Module(new SimpleBusCrossbarNto1(2))
40  cohMg.io.in <> noop.io.imem.mem
41  noop.io.dmem.coh <> cohMg.io.out.coh
42  xbar.io.in(0) <> cohMg.io.out.mem
43  xbar.io.in(1) <> noop.io.dmem.mem
44
45  val axi2sb = Module(new AXI42SimpleBusConverter())
46  axi2sb.io.in <> io.frontend
47  noop.io.frontend <> axi2sb.io.out
48
49  if (HasL2cache) {
50    val l2cacheOut = Wire(new SimpleBusC)
51    val l2cacheIn = if (HasPrefetch) {
52      val prefetcher = Module(new Prefetcher)
53      val l2cacheIn = Wire(new SimpleBusUC)
54      prefetcher.io.in <> xbar.io.out.req
55      l2cacheIn.req <> prefetcher.io.out
56      xbar.io.out.resp <> l2cacheIn.resp
57      l2cacheIn
58    } else xbar.io.out
59    val l2Empty = Wire(Bool())
60    l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC) :: Nil, flush = "b00".U, empty = l2Empty, enable = true)(
61      CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
62    io.mem <> l2cacheOut.mem.toAXI4()
63    l2cacheOut.coh.resp.ready := true.B
64    l2cacheOut.coh.req.valid := false.B
65    l2cacheOut.coh.req.bits := DontCare
66  } else {
67    io.mem <> xbar.io.out.toAXI4()
68  }
69
70  noop.io.imem.coh.resp.ready := true.B
71  noop.io.imem.coh.req.valid := false.B
72  noop.io.imem.coh.req.bits := DontCare
73
74  val addrSpace = List(
75    (0x40000000L, 0x08000000L), // external devices
76    (0x48000000L, 0x00010000L)  // CLINT
77  )
78  val mmioXbar = Module(new SimpleBusCrossbar1toN(addrSpace))
79  mmioXbar.io.in <> noop.io.mmio
80
81  val extDev = mmioXbar.io.out(0)
82  val clint = Module(new AXI4Timer(sim = !p.FPGAPlatform))
83  clint.io.in <> mmioXbar.io.out(1).toAXI4Lite()
84  if (p.FPGAPlatform) io.mmio <> extDev.toAXI4Lite()
85  else io.mmio <> extDev
86
87  //val mtipSync = RegNext(RegNext(io.mtip))
88  val mtipSync = clint.io.extra.get.mtip
89  val meipSync = RegNext(RegNext(io.meip))
90  BoringUtils.addSource(mtipSync, "mtip")
91  BoringUtils.addSource(meipSync, "meip")
92
93  // ILA
94  if (p.FPGAPlatform) {
95    def BoringUtilsConnect(sink: UInt, id: String) {
96      val temp = WireInit(0.U(64.W))
97      BoringUtils.addSink(temp, id)
98      sink := temp
99    }
100
101    val dummy = WireInit(0.U.asTypeOf(new ILABundle))
102    val ila = io.ila.getOrElse(dummy)
103    BoringUtilsConnect(ila.WBUpc      ,"ilaWBUpc")
104    BoringUtilsConnect(ila.WBUvalid   ,"ilaWBUvalid")
105    BoringUtilsConnect(ila.WBUrfWen   ,"ilaWBUrfWen")
106    BoringUtilsConnect(ila.WBUrfDest  ,"ilaWBUrfDest")
107    BoringUtilsConnect(ila.WBUrfData  ,"ilaWBUrfData")
108    BoringUtilsConnect(ila.InstrCnt   ,"ilaInstrCnt")
109  }
110}
111