xref: /XiangShan/src/main/scala/system/SoC.scala (revision 195ef4a53ab54326d879e884c4e1568f424f2668) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.tilelink._
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
28import freechips.rocketchip.tilelink._
29import huancun._
30import top.BusPerfMonitor
31import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
32import xiangshan.backend.fu.PMAConst
33import xiangshan.{DebugOptionsKey, XSTileKey}
34import coupledL2.EnableCHI
35
36case object SoCParamsKey extends Field[SoCParameters]
37
38case class SoCParameters
39(
40  EnableILA: Boolean = false,
41  PAddrBits: Int = 36,
42  extIntrs: Int = 64,
43  L3NBanks: Int = 4,
44  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
45    name = "L3",
46    level = 3,
47    ways = 8,
48    sets = 2048 // 1MB per bank
49  )),
50  XSTopPrefix: Option[String] = None,
51  NodeIDWidth: Int = 7
52){
53  // L3 configurations
54  val L3InnerBusWidth = 256
55  val L3BlockSize = 64
56  // on chip network configurations
57  val L3OuterBusWidth = 256
58}
59
60trait HasSoCParameter {
61  implicit val p: Parameters
62
63  val soc = p(SoCParamsKey)
64  val debugOpts = p(DebugOptionsKey)
65  val tiles = p(XSTileKey)
66
67  val NumCores = tiles.size
68  val EnableILA = soc.EnableILA
69
70  // L3 configurations
71  val L3InnerBusWidth = soc.L3InnerBusWidth
72  val L3BlockSize = soc.L3BlockSize
73  val L3NBanks = soc.L3NBanks
74
75  // on chip network configurations
76  val L3OuterBusWidth = soc.L3OuterBusWidth
77
78  val NrExtIntr = soc.extIntrs
79}
80
81class ILABundle extends Bundle {}
82
83
84abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
85  val bankedNode = BankBinder(L3NBanks, L3BlockSize)
86  val peripheralXbar = TLXbar()
87  val l3_xbar = TLXbar()
88  val l3_banked_xbar = TLXbar()
89}
90
91// We adapt the following three traits from rocket-chip.
92// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
93trait HaveSlaveAXI4Port {
94  this: BaseSoC =>
95
96  val idBits = 14
97
98  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
99    Seq(AXI4MasterParameters(
100      name = "dma",
101      id = IdRange(0, 1 << idBits)
102    ))
103  )))
104  private val errorDevice = LazyModule(new TLError(
105    params = DevNullParams(
106      address = Seq(AddressSet(0x0, 0x7fffffffL)),
107      maxAtomic = 8,
108      maxTransfer = 64),
109    beatBytes = L3InnerBusWidth / 8
110  ))
111  private val error_xbar = TLXbar()
112
113  l3_xbar :=
114    TLFIFOFixer() :=
115    TLWidthWidget(32) :=
116    AXI4ToTL() :=
117    AXI4UserYanker(Some(1)) :=
118    AXI4Fragmenter() :=
119    AXI4Buffer() :=
120    AXI4Buffer() :=
121    AXI4IdIndexer(1) :=
122    l3FrontendAXI4Node
123  errorDevice.node := l3_xbar
124
125  val dma = InModuleBody {
126    l3FrontendAXI4Node.makeIOs()
127  }
128}
129
130trait HaveAXI4MemPort {
131  this: BaseSoC =>
132  val device = new MemoryDevice
133  // 36-bit physical address
134  val memRange = AddressSet(0x00000000L, 0xfffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
135  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
136    AXI4SlavePortParameters(
137      slaves = Seq(
138        AXI4SlaveParameters(
139          address = memRange,
140          regionType = RegionType.UNCACHED,
141          executable = true,
142          supportsRead = TransferSizes(1, L3BlockSize),
143          supportsWrite = TransferSizes(1, L3BlockSize),
144          interleavedId = Some(0),
145          resources = device.reg("mem")
146        )
147      ),
148      beatBytes = L3OuterBusWidth / 8,
149      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
150    )
151  ))
152
153  val mem_xbar = TLXbar()
154  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform, stat_latency = true)
155  mem_xbar :=*
156    TLBuffer.chainNode(2) :=
157    TLCacheCork() :=
158    l3_mem_pmu :=
159    TLClientsMerger() :=
160    TLXbar() :=*
161    bankedNode
162
163  mem_xbar :=
164    TLWidthWidget(8) :=
165    TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
166    peripheralXbar
167
168  memAXI4SlaveNode :=
169    AXI4Buffer() :=
170    AXI4Buffer() :=
171    AXI4Buffer() :=
172    AXI4IdIndexer(idBits = 14) :=
173    AXI4UserYanker() :=
174    AXI4Deinterleaver(L3BlockSize) :=
175    TLToAXI4() :=
176    TLSourceShrinker(64) :=
177    TLWidthWidget(L3OuterBusWidth / 8) :=
178    TLBuffer.chainNode(2) :=
179    mem_xbar
180
181  val memory = InModuleBody {
182    memAXI4SlaveNode.makeIOs()
183  }
184}
185
186trait HaveAXI4PeripheralPort { this: BaseSoC =>
187  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
188  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
189  val uartRange = AddressSet(0x40600000, 0xf)
190  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
191  val uartParams = AXI4SlaveParameters(
192    address = Seq(uartRange),
193    regionType = RegionType.UNCACHED,
194    supportsRead = TransferSizes(1, 8),
195    supportsWrite = TransferSizes(1, 8),
196    resources = uartDevice.reg
197  )
198  val peripheralRange = AddressSet(
199    0x0, 0x7fffffff
200  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
201  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
202    Seq(AXI4SlaveParameters(
203      address = peripheralRange,
204      regionType = RegionType.UNCACHED,
205      supportsRead = TransferSizes(1, 8),
206      supportsWrite = TransferSizes(1, 8),
207      interleavedId = Some(0)
208    ), uartParams),
209    beatBytes = 8
210  )))
211
212  peripheralNode :=
213    AXI4UserYanker() :=
214    AXI4IdIndexer(idBits = 2) :=
215    AXI4Buffer() :=
216    AXI4Buffer() :=
217    AXI4Buffer() :=
218    AXI4Buffer() :=
219    AXI4UserYanker() :=
220    AXI4Deinterleaver(8) :=
221    TLToAXI4() :=
222    TLBuffer.chainNode(3) :=
223    peripheralXbar
224
225  val peripheral = InModuleBody {
226    peripheralNode.makeIOs()
227  }
228
229}
230
231class MemMisc()(implicit p: Parameters) extends BaseSoC
232  with HaveAXI4MemPort
233  with PMAConst
234{
235  val enableCHI = p(EnableCHI)
236
237  val peripheral_ports = Array.fill(NumCores) { TLTempNode() }
238  val core_to_l3_ports = if (enableCHI) None else Some(Array.fill(NumCores) { TLTempNode() })
239
240  val l3_in = TLTempNode()
241  val l3_out = TLTempNode()
242
243  l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar
244  bankedNode :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
245
246  if(soc.L3CacheParamsOpt.isEmpty){
247    l3_out :*= l3_in
248  }
249
250  for(port <- peripheral_ports) {
251    peripheralXbar := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
252  }
253
254  core_to_l3_ports.foreach { case _ =>
255    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
256      l3_banked_xbar :=*
257        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
258        TLBuffer() :=
259        core_out
260    }
261  }
262  l3_banked_xbar := TLBuffer.chainNode(2) := l3_xbar
263
264  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
265  clint.node := peripheralXbar
266
267  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
268    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
269    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
270      val in = IO(Input(Vec(num, Bool())))
271      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
272    }
273    lazy val module = new IntSourceNodeToModuleImp(this)
274  }
275
276  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
277  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
278
279  plic.intnode := plicSource.sourceNode
280  plic.node := peripheralXbar
281
282  val pll_node = TLRegisterNode(
283    address = Seq(AddressSet(0x3a000000L, 0xfff)),
284    device = new SimpleDevice("pll_ctrl", Seq()),
285    beatBytes = 8,
286    concurrency = 1
287  )
288  pll_node := peripheralXbar
289
290  val debugModule = LazyModule(new DebugModule(NumCores)(p))
291  debugModule.debug.node := peripheralXbar
292  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
293    l3_xbar := TLBuffer() := sb2tl.node
294  }
295
296  val pma = LazyModule(new TLPMA)
297  pma.node :=
298    TLBuffer.chainNode(4) :=
299    peripheralXbar
300
301  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
302
303    val debug_module_io = IO(new debugModule.DebugModuleIO)
304    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
305    val rtc_clock = IO(Input(Bool()))
306    val pll0_lock = IO(Input(Bool()))
307    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
308    val cacheable_check = IO(new TLPMAIO)
309
310    debugModule.module.io <> debug_module_io
311
312    // sync external interrupts
313    require(plicSource.module.in.length == ext_intrs.getWidth)
314    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
315      val ext_intr_sync = RegInit(0.U(3.W))
316      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
317      plic_in := ext_intr_sync(2)
318    }
319
320    pma.module.io <> cacheable_check
321
322    // positive edge sampling of the lower-speed rtc_clock
323    val rtcTick = RegInit(0.U(3.W))
324    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
325    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
326
327    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
328    val pll_lock = RegNext(next = pll0_lock, init = false.B)
329
330    pll0_ctrl <> VecInit(pll_ctrl_regs)
331
332    pll_node.regmap(
333      0x000 -> RegFieldGroup(
334        "Pll", Some("PLL ctrl regs"),
335        pll_ctrl_regs.zipWithIndex.map{
336          case (r, i) => RegField(32, r, RegFieldDesc(
337            s"PLL_ctrl_$i",
338            desc = s"PLL ctrl register #$i"
339          ))
340        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
341          "PLL_lock",
342          "PLL lock register"
343        ))
344      )
345    )
346  }
347
348  lazy val module = new SoCMiscImp(this)
349}
350class SoCMisc()(implicit p: Parameters) extends MemMisc
351  with HaveAXI4PeripheralPort
352  with HaveSlaveAXI4Port
353
354