xref: /XiangShan/src/main/scala/system/SoC.scala (revision 09606cfd39875f8e3b3f54f4d2635a66774c4848) 
1package system
2
3import noop._
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10
11trait HasSoCParameter {
12  val EnableILA = false
13  val HasL2cache = true
14  val HasPrefetch = false
15}
16
17class ILABundle extends Bundle {
18  val WBUpc = UInt(32.W)
19  val WBUvalid = UInt(1.W)
20  val WBUrfWen = UInt(1.W)
21  val WBUrfDest = UInt(5.W)
22  val WBUrfData = UInt(64.W)
23  val InstrCnt = UInt(64.W)
24}
25
26class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
27  val io = IO(new Bundle{
28    val mem = new AXI4
29    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
30    val mtip = Input(Bool())
31    val meip = Input(Bool())
32    val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
33  })
34
35  val noop = Module(new NOOP)
36  val cohMg = Module(new CoherenceManager)
37  val xbar = Module(new SimpleBusCrossbarNto1(2))
38  cohMg.io.in <> noop.io.imem.mem
39  noop.io.dmem.coh <> cohMg.io.out.coh
40  xbar.io.in(0) <> cohMg.io.out.mem
41  xbar.io.in(1) <> noop.io.dmem.mem
42
43  if (HasL2cache) {
44    val l2cacheOut = Wire(new SimpleBusC)
45    val l2cacheIn = if (HasPrefetch) {
46      val prefetcher = Module(new Prefetcher)
47      prefetcher.io.in <> noop.io.prefetchReq
48      val l2cacheIn = Wire(new SimpleBusUC)
49      val l2cacheInReqArb = Module(new Arbiter(chiselTypeOf(noop.io.prefetchReq.bits), 2))
50      l2cacheInReqArb.io.in(0) <> xbar.io.out.req
51      l2cacheInReqArb.io.in(1) <> prefetcher.io.out
52      l2cacheIn.req <> l2cacheInReqArb.io.out
53      xbar.io.out.resp <> l2cacheIn.resp
54      l2cacheIn
55    } else xbar.io.out
56    l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(
57      CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
58    io.mem <> l2cacheOut.mem.toAXI4()
59    l2cacheOut.coh.resp.ready := true.B
60    l2cacheOut.coh.req.valid := false.B
61    l2cacheOut.coh.req.bits := DontCare
62  } else {
63    io.mem <> xbar.io.out.toAXI4()
64  }
65
66  if (!HasPrefetch) {
67    noop.io.prefetchReq.ready := true.B
68  }
69
70  noop.io.imem.coh.resp.ready := true.B
71  noop.io.imem.coh.req.valid := false.B
72  noop.io.imem.coh.req.bits := DontCare
73
74  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
75  else io.mmio <> noop.io.mmio
76
77  val mtipSync = RegNext(RegNext(io.mtip))
78  val meipSync = RegNext(RegNext(io.meip))
79  BoringUtils.addSource(mtipSync, "mtip")
80  BoringUtils.addSource(meipSync, "meip")
81
82  // ILA
83  if (p.FPGAPlatform) {
84    def BoringUtilsConnect(sink: UInt, id: String) {
85      val temp = WireInit(0.U(64.W))
86      BoringUtils.addSink(temp, id)
87      sink := temp
88    }
89
90    val dummy = WireInit(0.U.asTypeOf(new ILABundle))
91    val ila = io.ila.getOrElse(dummy)
92    BoringUtilsConnect(ila.WBUpc      ,"ilaWBUpc")
93    BoringUtilsConnect(ila.WBUvalid   ,"ilaWBUvalid")
94    BoringUtilsConnect(ila.WBUrfWen   ,"ilaWBUrfWen")
95    BoringUtilsConnect(ila.WBUrfDest  ,"ilaWBUrfDest")
96    BoringUtilsConnect(ila.WBUrfData  ,"ilaWBUrfData")
97    BoringUtilsConnect(ila.InstrCnt   ,"ilaInstrCnt")
98  }
99}
100