1006e1884SZihao Yupackage system 2006e1884SZihao Yu 32225d46eSJiawei Linimport chipsalliance.rocketchip.config.{Field, Parameters} 4006e1884SZihao Yuimport chisel3._ 5096ea47eSzhanglinjuanimport chisel3.util._ 62225d46eSJiawei Linimport xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters} 70584d3a8SLinJiaweiimport freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors} 8a428082bSLinJiawei 92225d46eSJiawei Lincase object SoCParamsKey extends Field[SoCParameters] 102225d46eSJiawei Lin 11a428082bSLinJiaweicase class SoCParameters 12a428082bSLinJiawei( 132225d46eSJiawei Lin cores: List[XSCoreParameters], 14a428082bSLinJiawei EnableILA: Boolean = false, 152225d46eSJiawei Lin extIntrs: Int = 150 162225d46eSJiawei Lin){ 172225d46eSJiawei Lin val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y) 182225d46eSJiawei Lin // L3 configurations 19*9d5a2027SYinan Xu val useFakeL3Cache = false 202225d46eSJiawei Lin val L3InnerBusWidth = 256 212225d46eSJiawei Lin val L3Size = 4 * 1024 * 1024 // 4MB 222225d46eSJiawei Lin val L3BlockSize = 64 232225d46eSJiawei Lin val L3NBanks = 4 242225d46eSJiawei Lin val L3NWays = 8 25006e1884SZihao Yu 262225d46eSJiawei Lin // on chip network configurations 272225d46eSJiawei Lin val L3OuterBusWidth = 256 282225d46eSJiawei Lin 292225d46eSJiawei Lin} 302225d46eSJiawei Lin 312225d46eSJiawei Lintrait HasSoCParameter { 322225d46eSJiawei Lin implicit val p: Parameters 332225d46eSJiawei Lin 342225d46eSJiawei Lin val soc = p(SoCParamsKey) 352225d46eSJiawei Lin val debugOpts = p(DebugOptionsKey) 362225d46eSJiawei Lin val NumCores = soc.cores.size 37a428082bSLinJiawei val EnableILA = soc.EnableILA 382225d46eSJiawei Lin 392225d46eSJiawei Lin // L3 configurations 40*9d5a2027SYinan Xu val useFakeL3Cache = soc.useFakeL3Cache 412225d46eSJiawei Lin val L3InnerBusWidth = soc.L3InnerBusWidth 422225d46eSJiawei Lin val L3Size = soc.L3Size 432225d46eSJiawei Lin val L3BlockSize = soc.L3BlockSize 442225d46eSJiawei Lin val L3NBanks = soc.L3NBanks 452225d46eSJiawei Lin val L3NWays = soc.L3NWays 462225d46eSJiawei Lin val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 472225d46eSJiawei Lin 482225d46eSJiawei Lin // on chip network configurations 492225d46eSJiawei Lin val L3OuterBusWidth = soc.L3OuterBusWidth 502225d46eSJiawei Lin 512225d46eSJiawei Lin val NrExtIntr = soc.extIntrs 52303b861dSZihao Yu} 53303b861dSZihao Yu 541e3fad10SLinJiaweiclass ILABundle extends Bundle {} 55303b861dSZihao Yu 563e586e47Slinjiawei 572225d46eSJiawei Linclass L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 582225d46eSJiawei Lin val paddr = Valid(UInt(soc.PAddrBits.W)) 590584d3a8SLinJiawei // for now, we only detect ecc 600584d3a8SLinJiawei val ecc_error = Valid(Bool()) 613e586e47Slinjiawei} 623e586e47Slinjiawei 632225d46eSJiawei Linclass XSL1BusErrors(val nCores: Int)(implicit val p: Parameters) extends BusErrors { 649637c0c6SLinJiawei val icache = Vec(nCores, new L1CacheErrorInfo) 654e3ce935Sljw val l1plus = Vec(nCores, new L1CacheErrorInfo) 669637c0c6SLinJiawei val dcache = Vec(nCores, new L1CacheErrorInfo) 679637c0c6SLinJiawei 689637c0c6SLinJiawei override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] = 699637c0c6SLinJiawei List.tabulate(nCores){i => 709637c0c6SLinJiawei List( 719637c0c6SLinJiawei Some(icache(i).paddr, s"IBUS_$i", s"Icache_$i bus error"), 729637c0c6SLinJiawei Some(icache(i).ecc_error, s"I_ECC_$i", s"Icache_$i ecc error"), 734e3ce935Sljw Some(l1plus(i).paddr, s"L1PLUS_$i", s"L1PLUS_$i bus error"), 744e3ce935Sljw Some(l1plus(i).ecc_error, s"L1PLUS_ECC_$i", s"L1PLUS_$i ecc error"), 759637c0c6SLinJiawei Some(dcache(i).paddr, s"DBUS_$i", s"Dcache_$i bus error"), 769637c0c6SLinJiawei Some(dcache(i).ecc_error, s"D_ECC_$i", s"Dcache_$i ecc error") 770584d3a8SLinJiawei ) 789637c0c6SLinJiawei }.flatten 790584d3a8SLinJiawei} 80