xref: /XiangShan/src/main/scala/system/SoC.scala (revision 5704b623ceb4fd3ffad4b285e8aab19175f40feb)

package system

import noop.{NOOP, NOOPConfig, Cache, L2Cache, CacheConfig}
import bus.axi4.{AXI4, AXI4Lite}
import bus.simplebus._

import chisel3._
import chisel3.util.experimental.BoringUtils

class NOOPSoC(implicit val p: NOOPConfig) extends Module {
  val io = IO(new Bundle{
    val mem = new AXI4
    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
    val mtip = Input(Bool())
    val meip = Input(Bool())
  })

  val noop = Module(new NOOP)
  val cohMg = Module(new CoherenceInterconnect)
  cohMg.io.in(0) <> noop.io.imem
  cohMg.io.in(1) <> noop.io.dmem
  // io.mem <> cohMg.io.out.toAXI4()
	val mmioXbar = Module(new SimpleBusCrossbarNto1(2))

	val l2cacheOut = Wire(new SimpleBusUC)
	l2cacheOut <> Cache(in = cohMg.io.out, mmio = mmioXbar.io.in(0), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
	io.mem <> l2cacheOut.toAXI4()
	/*
	val l2cache = Module(new L2Cache)
	l2cache.io.in <> cohMg.io.out
	mmioXbar.io.in(0) <> l2cache.io.mmio
	l2cache.io.flush := "b00".U
	io.mem <> l2cache.io.out.toAXI4()
	*/

	mmioXbar.io.in(1) <> noop.io.mmio
	if (p.FPGAPlatform) io.mmio <> mmioXbar.io.out.toAXI4Lite()
  else io.mmio <> mmioXbar.io.out
	/*
  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
  else io.mmio <> noop.io.mmio
	*/
  val mtipSync = RegNext(RegNext(io.mtip))
  val meipSync = RegNext(RegNext(io.meip))
  BoringUtils.addSource(mtipSync, "mtip")
  BoringUtils.addSource(meipSync, "meip")
}