1006e1884SZihao Yupackage system 2006e1884SZihao Yu 3006e1884SZihao Yuimport noop.{NOOP, NOOPConfig} 4006e1884SZihao Yuimport bus.axi4.{AXI4, AXI4Lite} 58f36f779SZihao Yuimport bus.simplebus._ 6006e1884SZihao Yu 7006e1884SZihao Yuimport chisel3._ 8fe820c3dSZihao Yuimport chisel3.util.experimental.BoringUtils 9006e1884SZihao Yu 10*303b861dSZihao Yutrait HasILAParameter { 11*303b861dSZihao Yu val enableILA = false 12*303b861dSZihao Yu} 13*303b861dSZihao Yu 14*303b861dSZihao Yuclass ILABundle extends Bundle { 15*303b861dSZihao Yu val WBUpc = UInt(32.W) 16*303b861dSZihao Yu val WBUvalid = UInt(1.W) 17*303b861dSZihao Yu val WBUrfWen = UInt(1.W) 18*303b861dSZihao Yu val WBUrfDest = UInt(5.W) 19*303b861dSZihao Yu val WBUrfData = UInt(64.W) 20*303b861dSZihao Yu val InstrCnt = UInt(64.W) 21*303b861dSZihao Yu} 22*303b861dSZihao Yu 23*303b861dSZihao Yuclass NOOPSoC(implicit val p: NOOPConfig) extends Module with HasILAParameter { 24006e1884SZihao Yu val io = IO(new Bundle{ 25cdd59e9fSZihao Yu val mem = new AXI4 26ad255e6cSZihao Yu val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC }) 27fe820c3dSZihao Yu val mtip = Input(Bool()) 28466eb0a8SZihao Yu val meip = Input(Bool()) 29*303b861dSZihao Yu val ila = if (p.FPGAPlatform && enableILA) Some(Output(new ILABundle)) else None 30006e1884SZihao Yu }) 31006e1884SZihao Yu 32006e1884SZihao Yu val noop = Module(new NOOP) 33635253aaSZihao Yu val cohMg = Module(new CoherenceManager) 34635253aaSZihao Yu val xbar = Module(new SimpleBusCrossbarNto1(2)) 35635253aaSZihao Yu cohMg.io.in <> noop.io.imem.mem 36635253aaSZihao Yu noop.io.dmem.coh <> cohMg.io.out.coh 37635253aaSZihao Yu xbar.io.in(0) <> cohMg.io.out.mem 38635253aaSZihao Yu xbar.io.in(1) <> noop.io.dmem.mem 39635253aaSZihao Yu io.mem <> xbar.io.out.toAXI4() 40635253aaSZihao Yu 41635253aaSZihao Yu noop.io.imem.coh.resp.ready := true.B 42635253aaSZihao Yu noop.io.imem.coh.req.valid := false.B 43635253aaSZihao Yu noop.io.imem.coh.req.bits := DontCare 44006e1884SZihao Yu 45ad255e6cSZihao Yu if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite() 46006e1884SZihao Yu else io.mmio <> noop.io.mmio 47fe820c3dSZihao Yu 485d41d760SZihao Yu val mtipSync = RegNext(RegNext(io.mtip)) 49466eb0a8SZihao Yu val meipSync = RegNext(RegNext(io.meip)) 505d41d760SZihao Yu BoringUtils.addSource(mtipSync, "mtip") 51466eb0a8SZihao Yu BoringUtils.addSource(meipSync, "meip") 52*303b861dSZihao Yu 53*303b861dSZihao Yu // ILA 54*303b861dSZihao Yu if (p.FPGAPlatform) { 55*303b861dSZihao Yu def BoringUtilsConnect(sink: UInt, id: String) { 56*303b861dSZihao Yu val temp = WireInit(0.U(64.W)) 57*303b861dSZihao Yu BoringUtils.addSink(temp, id) 58*303b861dSZihao Yu sink := temp 59*303b861dSZihao Yu } 60*303b861dSZihao Yu 61*303b861dSZihao Yu val dummy = WireInit(0.U.asTypeOf(new ILABundle)) 62*303b861dSZihao Yu val ila = io.ila.getOrElse(dummy) 63*303b861dSZihao Yu BoringUtilsConnect(ila.WBUpc ,"ilaWBUpc") 64*303b861dSZihao Yu BoringUtilsConnect(ila.WBUvalid ,"ilaWBUvalid") 65*303b861dSZihao Yu BoringUtilsConnect(ila.WBUrfWen ,"ilaWBUrfWen") 66*303b861dSZihao Yu BoringUtilsConnect(ila.WBUrfDest ,"ilaWBUrfDest") 67*303b861dSZihao Yu BoringUtilsConnect(ila.WBUrfData ,"ilaWBUrfData") 68*303b861dSZihao Yu BoringUtilsConnect(ila.InstrCnt ,"ilaInstrCnt") 69*303b861dSZihao Yu } 70006e1884SZihao Yu} 71