1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package device.standalone 18 19import chisel3._ 20import freechips.rocketchip.diplomacy._ 21import org.chipsalliance.cde.config.Parameters 22import freechips.rocketchip.devices.tilelink._ 23import freechips.rocketchip.interrupts._ 24 25class StandAlonePLIC ( 26 useTL: Boolean = false, 27 baseAddress: BigInt, 28 addrWidth: Int, 29 dataWidth: Int = 64, 30 hartNum: Int 31)(implicit p: Parameters) extends StandAloneDevice( 32 useTL, baseAddress, addrWidth, dataWidth, hartNum 33) with BindingScope { 34 35 private def plicParam = PLICParams(baseAddress) 36 def addressSet: AddressSet = plicParam.address 37 38 private val plic = LazyModule(new TLPLIC(plicParam, dataWidth / 8)) 39 plic.node := xbar 40 41 // interrupts 42 val plicIntNode = IntSinkNode(IntSinkPortSimple(hartNum * 2, 1)) 43 plicIntNode :*= plic.intnode 44 val int = InModuleBody(plicIntNode.makeIOs()) 45 46} 47