1*720dd621STang Haojin/*************************************************************************************** 2*720dd621STang Haojin* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3*720dd621STang Haojin* Copyright (c) 2020-2021 Peng Cheng Laboratory 4*720dd621STang Haojin* 5*720dd621STang Haojin* XiangShan is licensed under Mulan PSL v2. 6*720dd621STang Haojin* You can use this software according to the terms and conditions of the Mulan PSL v2. 7*720dd621STang Haojin* You may obtain a copy of Mulan PSL v2 at: 8*720dd621STang Haojin* http://license.coscl.org.cn/MulanPSL2 9*720dd621STang Haojin* 10*720dd621STang Haojin* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11*720dd621STang Haojin* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12*720dd621STang Haojin* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13*720dd621STang Haojin* 14*720dd621STang Haojin* See the Mulan PSL v2 for more details. 15*720dd621STang Haojin***************************************************************************************/ 16*720dd621STang Haojin 17*720dd621STang Haojinpackage device.standalone 18*720dd621STang Haojin 19*720dd621STang Haojinimport chisel3._ 20*720dd621STang Haojinimport freechips.rocketchip.diplomacy._ 21*720dd621STang Haojinimport org.chipsalliance.cde.config.Parameters 22*720dd621STang Haojinimport freechips.rocketchip.devices.tilelink._ 23*720dd621STang Haojinimport freechips.rocketchip.interrupts._ 24*720dd621STang Haojin 25*720dd621STang Haojinclass StandAlonePLIC ( 26*720dd621STang Haojin useTL: Boolean = false, 27*720dd621STang Haojin baseAddress: BigInt, 28*720dd621STang Haojin addrWidth: Int, 29*720dd621STang Haojin dataWidth: Int = 64, 30*720dd621STang Haojin hartNum: Int 31*720dd621STang Haojin)(implicit p: Parameters) extends StandAloneDevice( 32*720dd621STang Haojin useTL, baseAddress, addrWidth, dataWidth, hartNum 33*720dd621STang Haojin) with BindingScope { 34*720dd621STang Haojin 35*720dd621STang Haojin private def plicParam = PLICParams(baseAddress) 36*720dd621STang Haojin def addressSet: AddressSet = plicParam.address 37*720dd621STang Haojin 38*720dd621STang Haojin private val plic = LazyModule(new TLPLIC(plicParam, dataWidth / 8)) 39*720dd621STang Haojin plic.node := xbar 40*720dd621STang Haojin 41*720dd621STang Haojin // interrupts 42*720dd621STang Haojin val plicIntNode = IntSinkNode(IntSinkPortSimple(hartNum * 2, 1)) 43*720dd621STang Haojin plicIntNode :*= plic.intnode 44*720dd621STang Haojin val int = InModuleBody(plicIntNode.makeIOs()) 45*720dd621STang Haojin 46*720dd621STang Haojin} 47