1720dd621STang Haojin/*************************************************************************************** 2720dd621STang Haojin* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3720dd621STang Haojin* Copyright (c) 2020-2021 Peng Cheng Laboratory 4720dd621STang Haojin* 5720dd621STang Haojin* XiangShan is licensed under Mulan PSL v2. 6720dd621STang Haojin* You can use this software according to the terms and conditions of the Mulan PSL v2. 7720dd621STang Haojin* You may obtain a copy of Mulan PSL v2 at: 8720dd621STang Haojin* http://license.coscl.org.cn/MulanPSL2 9720dd621STang Haojin* 10720dd621STang Haojin* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11720dd621STang Haojin* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12720dd621STang Haojin* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13720dd621STang Haojin* 14720dd621STang Haojin* See the Mulan PSL v2 for more details. 15720dd621STang Haojin***************************************************************************************/ 16720dd621STang Haojin 17720dd621STang Haojinpackage device.standalone 18720dd621STang Haojin 19720dd621STang Haojinimport chisel3._ 20720dd621STang Haojinimport freechips.rocketchip.diplomacy._ 21720dd621STang Haojinimport org.chipsalliance.cde.config.Parameters 22720dd621STang Haojinimport freechips.rocketchip.devices.tilelink._ 23720dd621STang Haojinimport freechips.rocketchip.interrupts._ 24*2f9ea954STang Haojinimport utility.IntBuffer 25720dd621STang Haojin 26720dd621STang Haojinclass StandAlonePLIC ( 27720dd621STang Haojin useTL: Boolean = false, 28720dd621STang Haojin baseAddress: BigInt, 29720dd621STang Haojin addrWidth: Int, 30720dd621STang Haojin dataWidth: Int = 64, 31720dd621STang Haojin hartNum: Int 32720dd621STang Haojin)(implicit p: Parameters) extends StandAloneDevice( 33720dd621STang Haojin useTL, baseAddress, addrWidth, dataWidth, hartNum 34720dd621STang Haojin) with BindingScope { 35720dd621STang Haojin 36720dd621STang Haojin private def plicParam = PLICParams(baseAddress) 37720dd621STang Haojin def addressSet: AddressSet = plicParam.address 38720dd621STang Haojin 39720dd621STang Haojin private val plic = LazyModule(new TLPLIC(plicParam, dataWidth / 8)) 40720dd621STang Haojin plic.node := xbar 41720dd621STang Haojin 42720dd621STang Haojin // interrupts 43720dd621STang Haojin val plicIntNode = IntSinkNode(IntSinkPortSimple(hartNum * 2, 1)) 44*2f9ea954STang Haojin plicIntNode :*= IntBuffer() :*= plic.intnode 45720dd621STang Haojin val int = InModuleBody(plicIntNode.makeIOs()) 46720dd621STang Haojin 47720dd621STang Haojin} 48