1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package device.standalone 18 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.diplomacy._ 22import org.chipsalliance.cde.config.Parameters 23import freechips.rocketchip.devices.debug.DebugModuleKey 24import freechips.rocketchip.devices.tilelink._ 25import freechips.rocketchip.interrupts._ 26import freechips.rocketchip.util.AsyncResetSynchronizerShiftReg 27import device.XSDebugModuleParams 28import system.SoCParamsKey 29import xiangshan.XSCoreParamsKey 30import xiangshan.XSTileKey 31import device.DebugModule 32import utility.{IntBuffer, RegNextN} 33 34class StandAloneDebugModule ( 35 useTL: Boolean = false, 36 baseAddress: BigInt, 37 addrWidth: Int, 38 dataWidth: Int = 64, 39 hartNum: Int 40)(implicit p: Parameters) extends StandAloneDevice( 41 useTL, baseAddress, addrWidth, dataWidth, hartNum 42) with HasMasterInterface { 43 44 def addressSet: AddressSet = p(DebugModuleKey).get.address 45 46 val debugModule = LazyModule(new DebugModule(hartNum)(p)) 47 debugModule.debug.node := xbar 48 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach(masternode := _.node) 49 50 // interrupts 51 val debugModuleIntNode = IntSinkNode(IntSinkPortSimple(hartNum, 1)) 52 debugModuleIntNode :*= IntBuffer() :*= debugModule.debug.dmOuter.dmOuter.intnode 53 val int = InModuleBody(debugModuleIntNode.makeIOs()) 54 55 class StandAloneDebugModuleImp(val outer: StandAloneDebugModule)(implicit p: Parameters) extends StandAloneDeviceRawImp(outer) { 56 val io = IO(new outer.debugModule.DebugModuleIO) 57 childClock := io.clock.asClock 58 childReset := io.reset.asAsyncReset 59 io <> outer.debugModule.module.io 60 outer.debugModule.module.io.reset := io.reset.asAsyncReset 61 outer.debugModule.module.io.debugIO.reset := io.debugIO.reset.asAsyncReset 62 outer.debugModule.module.io.debugIO.systemjtag.foreach(_.reset := io.debugIO.systemjtag.get.reset.asAsyncReset) 63 withClockAndReset(io.clock.asClock, io.reset.asAsyncReset) { 64 outer.debugModule.module.io.resetCtrl.hartIsInReset := AsyncResetSynchronizerShiftReg(io.resetCtrl.hartIsInReset, 3, 0) 65 io.resetCtrl.hartResetReq.foreach(req => 66 req := RegNext(outer.debugModule.module.io.resetCtrl.hartResetReq.get, 0.U.asTypeOf(req))) 67 } 68 } 69 70 override lazy val module = new StandAloneDebugModuleImp(this) 71 72} 73