xref: /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala (revision 3a3744e43e266ae0f7b9f454e4a97c2a46658401) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device.standalone
18
19import chisel3._
20import chisel3.util._
21import freechips.rocketchip.diplomacy._
22import org.chipsalliance.cde.config.Parameters
23import freechips.rocketchip.devices.debug.DebugModuleKey
24import freechips.rocketchip.devices.tilelink._
25import freechips.rocketchip.interrupts._
26import freechips.rocketchip.util.AsyncResetSynchronizerShiftReg
27import device.XSDebugModuleParams
28import system.SoCParamsKey
29import xiangshan.XSCoreParamsKey
30import xiangshan.XSTileKey
31import device.DebugModule
32import utility.{IntBuffer, RegNextN}
33
34class StandAloneDebugModule (
35  useTL: Boolean = false,
36  baseAddress: BigInt,
37  addrWidth: Int,
38  dataWidth: Int = 64,
39  hartNum: Int
40)(implicit p: Parameters) extends StandAloneDevice(
41  useTL, baseAddress, addrWidth, dataWidth, hartNum
42) with HasMasterInterface {
43
44  def masterAddrWidth: Int = 48
45
46  def addressSet: AddressSet = p(DebugModuleKey).get.address
47
48  val debugModule = LazyModule(new DebugModule(hartNum)(p))
49  debugModule.debug.node := xbar
50  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach(masternode := _.node)
51
52  // interrupts
53  val debugModuleIntNode = IntSinkNode(IntSinkPortSimple(hartNum, 1))
54  debugModuleIntNode :*= IntBuffer() :*= debugModule.debug.dmOuter.dmOuter.intnode
55  val int = InModuleBody(debugModuleIntNode.makeIOs())
56
57  class StandAloneDebugModuleImp(val outer: StandAloneDebugModule)(implicit p: Parameters) extends StandAloneDeviceRawImp(outer) {
58    val io = IO(new outer.debugModule.DebugModuleIO)
59    childClock := io.clock.asClock
60    childReset := io.reset.asAsyncReset
61    io <> outer.debugModule.module.io
62    outer.debugModule.module.io.reset := io.reset.asAsyncReset
63    outer.debugModule.module.io.debugIO.reset := io.debugIO.reset.asAsyncReset
64    outer.debugModule.module.io.debugIO.systemjtag.foreach(_.reset := io.debugIO.systemjtag.get.reset.asAsyncReset)
65    withClockAndReset(io.clock.asClock, io.reset.asAsyncReset) {
66      outer.debugModule.module.io.resetCtrl.hartIsInReset := AsyncResetSynchronizerShiftReg(io.resetCtrl.hartIsInReset, 3, 0)
67      io.resetCtrl.hartResetReq.foreach(req =>
68        req := RegNext(outer.debugModule.module.io.resetCtrl.hartResetReq.getOrElse(0.U.asTypeOf(req)), 0.U.asTypeOf(req)))
69    }
70  }
71
72  override lazy val module = new StandAloneDebugModuleImp(this)
73
74}
75