xref: /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala (revision 24bb726d80e7b0ea2ad2c685838b3a749ec0178d) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device.standalone
18
19import chisel3._
20import chisel3.util._
21import freechips.rocketchip.diplomacy._
22import org.chipsalliance.cde.config.Parameters
23import freechips.rocketchip.devices.tilelink._
24import freechips.rocketchip.interrupts._
25import device.XSDebugModuleParams
26import system.SoCParamsKey
27import xiangshan.XSCoreParamsKey
28import xiangshan.XSTileKey
29import device.DebugModule
30import utility.{IntBuffer, RegNextN}
31
32class StandAloneDebugModule (
33  useTL: Boolean = false,
34  baseAddress: BigInt,
35  addrWidth: Int,
36  dataWidth: Int = 64,
37  hartNum: Int
38)(implicit p: Parameters) extends StandAloneDevice(
39  useTL, baseAddress, addrWidth, dataWidth, hartNum
40) with HasMasterInterface {
41
42  def addressSet: AddressSet = AddressSet(XSDebugModuleParams.apply(p(XSTileKey).head.XLEN).baseAddress, 0xfff)
43
44  val debugModule = LazyModule(new DebugModule(hartNum)(p))
45  debugModule.debug.node := xbar
46  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach(masternode := _.node)
47
48  // interrupts
49  val debugModuleIntNode = IntSinkNode(IntSinkPortSimple(hartNum, 1))
50  debugModuleIntNode :*= IntBuffer() :*= debugModule.debug.dmOuter.dmOuter.intnode
51  val int = InModuleBody(debugModuleIntNode.makeIOs())
52
53  class StandAloneDebugModuleImp(val outer: StandAloneDebugModule)(implicit p: Parameters) extends StandAloneDeviceRawImp(outer) {
54    val io = IO(new outer.debugModule.DebugModuleIO)
55    childClock := io.clock.asClock
56    childReset := io.reset.asAsyncReset
57    io <> outer.debugModule.module.io
58    outer.debugModule.module.io.reset := io.reset.asAsyncReset
59    outer.debugModule.module.io.debugIO.reset := io.debugIO.reset.asAsyncReset
60    outer.debugModule.module.io.debugIO.systemjtag.foreach(_.reset := io.debugIO.systemjtag.get.reset.asAsyncReset)
61    withClockAndReset(io.clock.asClock, io.reset.asAsyncReset) {
62      outer.debugModule.module.io.resetCtrl.hartIsInReset :=
63        RegNextN(io.resetCtrl.hartIsInReset, 2, Some(0.U.asTypeOf(io.resetCtrl.hartIsInReset)))
64      io.resetCtrl.hartResetReq.foreach(req =>
65        req := RegNext(outer.debugModule.module.io.resetCtrl.hartResetReq.get, 0.U.asTypeOf(req)))
66    }
67  }
68
69  override lazy val module = new StandAloneDebugModuleImp(this)
70
71}
72