xref: /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala (revision 20957846171de148318edbfc667a5748881f7e03) 
1/***************************************************************************************
2* Copyright (c) 2024-2025 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024-2025 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device.standalone
18
19import chisel3._
20import chisel3.util._
21import freechips.rocketchip.diplomacy._
22import org.chipsalliance.cde.config.Parameters
23import freechips.rocketchip.devices.debug.DebugModuleKey
24import freechips.rocketchip.devices.tilelink._
25import freechips.rocketchip.interrupts._
26import freechips.rocketchip.util.AsyncResetSynchronizerShiftReg
27import system.SoCParamsKey
28import xiangshan.XSCoreParamsKey
29import xiangshan.XSTileKey
30import device.DebugModule
31import utility.{IntBuffer, RegNextN}
32
33class StandAloneDebugModule (
34  useTL: Boolean = false,
35  baseAddress: BigInt,
36  addrWidth: Int,
37  dataWidth: Int = 64,
38  hartNum: Int
39)(implicit p: Parameters) extends StandAloneDevice(
40  useTL, baseAddress, addrWidth, dataWidth, hartNum
41) with HasMasterInterface {
42
43  def masterAddrWidth: Int = 48
44
45  def addressSet: AddressSet = p(DebugModuleKey).get.address
46
47  val debugModule = LazyModule(new DebugModule(hartNum)(p))
48  debugModule.debug.node := xbar
49  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach(masternode := _.node)
50
51  // interrupts
52  val debugModuleIntNode = IntSinkNode(IntSinkPortSimple(hartNum, 1))
53  debugModuleIntNode :*= IntBuffer() :*= debugModule.debug.dmOuter.dmOuter.intnode
54  val int = InModuleBody(debugModuleIntNode.makeIOs())
55
56  class StandAloneDebugModuleImp(val outer: StandAloneDebugModule)(implicit p: Parameters) extends StandAloneDeviceRawImp(outer) {
57    val io = IO(new outer.debugModule.DebugModuleIO)
58    childClock := io.clock
59    childReset := io.reset.asAsyncReset
60    io <> outer.debugModule.module.io
61    outer.debugModule.module.io.reset := io.reset.asAsyncReset
62    outer.debugModule.module.io.debugIO.reset := io.debugIO.reset.asAsyncReset
63    outer.debugModule.module.io.debugIO.systemjtag.foreach(_.reset := io.debugIO.systemjtag.get.reset.asAsyncReset)
64    withClockAndReset(io.clock, io.reset.asAsyncReset) {
65      outer.debugModule.module.io.resetCtrl.hartIsInReset := AsyncResetSynchronizerShiftReg(io.resetCtrl.hartIsInReset, 3, 0)
66      io.resetCtrl.hartResetReq.foreach(req =>
67        req := RegNext(outer.debugModule.module.io.resetCtrl.hartResetReq.getOrElse(0.U.asTypeOf(req)), 0.U.asTypeOf(req)))
68    }
69  }
70
71  override lazy val module = new StandAloneDebugModuleImp(this)
72
73}
74