xref: /XiangShan/src/main/scala/device/RocketDebugWrapper.scala (revision d4aca96cccdcdafa80dd344996e18d1978a01af7) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chisel3._
20import xiangshan._
21import chisel3.experimental.{IntParam, noPrefix}
22import chisel3.util._
23import chisel3.util.HasBlackBoxResource
24import freechips.rocketchip.config.{Field, Parameters}
25import freechips.rocketchip.subsystem._
26import freechips.rocketchip.amba.apb._
27import freechips.rocketchip.diplomacy._
28import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalModuleTree
29import freechips.rocketchip.jtag._
30import freechips.rocketchip.util._
31import freechips.rocketchip.prci.{ClockSinkParameters, ClockSinkNode}
32import freechips.rocketchip.tilelink._
33import freechips.rocketchip.devices.debug.{JtagDTMConfig, TLDebugModule, DebugCustomXbar, ResetCtrlIO, DebugIO, SystemJTAGIO, DebugTransportModuleJTAG, PSDIO}
34import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
35import freechips.rocketchip.devices.debug._
36
37// this file uses code from rocketchip Periphery.scala
38// to simplify the code we remove options for apb, cjtag and dmi
39// this module creates wrapped dm and dtm
40
41class DebugModule(numCores: Int)(implicit p: Parameters) extends LazyModule {
42
43  val debug = LazyModule(new TLDebugModule(8)(p))
44
45//  debug.node := TLFragmenter() := peripheralXbar
46  val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
47  debug.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
48
49//  debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
50//    l2xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
51//  }
52  val fakeTreeNode = new GenericLogicalTreeNode
53  LogicalModuleTree.add(fakeTreeNode, debug.logicalTreeNode)
54
55  lazy val module = new LazyRawModuleImp(this) {
56    val io = IO(new Bundle{
57      val resetCtrl = new ResetCtrlIO(numCores)(p)
58      val debugIO = new DebugIO()(p)
59      val clock = Input(Bool())
60      val reset = Input(Bool())
61    })
62    debug.module.io.tl_reset := io.reset // this should be TL reset
63    debug.module.io.tl_clock := io.clock.asClock // this should be TL clock
64    debug.module.io.hartIsInReset := io.resetCtrl.hartIsInReset
65    io.resetCtrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }}
66
67    io.debugIO.clockeddmi.foreach { dbg => debug.module.io.dmi.get <> dbg } // not connected in current case since we use dtm
68    debug.module.io.debug_reset := io.debugIO.reset
69    debug.module.io.debug_clock := io.debugIO.clock
70    io.debugIO.ndreset := debug.module.io.ctrl.ndreset
71    io.debugIO.dmactive := debug.module.io.ctrl.dmactive
72    debug.module.io.ctrl.dmactiveAck := io.debugIO.dmactiveAck
73    io.debugIO.extTrigger.foreach { x => debug.module.io.extTrigger.foreach {y => x <> y}}
74    debug.module.io.ctrl.debugUnavail.foreach { _ := false.B }
75
76    val dtm = io.debugIO.systemjtag.map(instantiateJtagDTM(_))
77
78    def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = {
79      val c = new JtagDTMKeyDefault
80      val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, c))
81      dtm.io.jtag <> sj.jtag
82
83      io.debugIO.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS | x }  // force TMS high when debug is disabled
84
85      dtm.io.jtag_clock  := sj.jtag.TCK
86      dtm.io.jtag_reset  := sj.reset
87      dtm.io.jtag_mfr_id := sj.mfr_id
88      dtm.io.jtag_part_number := sj.part_number
89      dtm.io.jtag_version := sj.version
90      dtm.rf_reset := sj.reset
91      debug.module.io.dmi.get.dmi <> dtm.io.dmi
92      debug.module.io.dmi.get.dmiClock := sj.jtag.TCK
93      debug.module.io.dmi.get.dmiReset := sj.reset
94      dtm
95    }
96  }
97}
98
99object XSDebugModuleParams {
100
101  def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = {
102    new DebugModuleParams().copy(
103      nAbstractDataWords   = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4),
104      maxSupportedSBAccess = xlen,
105      hasBusMaster = true,
106      baseAddress = BigInt(0x38020000),
107      nScratch = 2
108    )
109  }
110}
111
112case object EnableJtag extends Field[Bool]
113
114class SimJTAG(tickDelay: Int = 50)(implicit val p: Parameters) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay)))
115  with HasBlackBoxResource {
116  val io = IO(new Bundle {
117    val clock = Input(Clock())
118    val reset = Input(Bool())
119    val jtag = new JTAGIO(hasTRSTn = true)
120    val enable = Input(Bool())
121    val init_done = Input(Bool())
122    val exit = Output(UInt(32.W))
123  })
124
125  def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
126    dutio.TCK := io.jtag.TCK
127    dutio.TMS := io.jtag.TMS
128    dutio.TDI := io.jtag.TDI
129    io.jtag.TDO := dutio.TDO
130
131    io.clock := tbclock
132    io.reset := tbreset
133
134    io.enable    := p(EnableJtag)
135    io.init_done := init_done
136
137    // Success is determined by the gdbserver
138    // which is controlling this simulation.
139    tbsuccess := io.exit === 1.U
140    when (io.exit >= 2.U) {
141      printf("*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
142      stop(1)
143    }
144  }
145}
146