1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package device 18 19import chisel3._ 20import xiangshan._ 21import chisel3.experimental.{ExtModule, IntParam, noPrefix} 22import chisel3.util._ 23import chisel3.util.HasExtModuleResource 24import freechips.rocketchip.config.{Field, Parameters} 25import freechips.rocketchip.subsystem._ 26import freechips.rocketchip.amba.apb._ 27import freechips.rocketchip.diplomacy._ 28import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalModuleTree 29import freechips.rocketchip.jtag._ 30import freechips.rocketchip.util._ 31import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters} 32import freechips.rocketchip.tilelink._ 33import freechips.rocketchip.devices.debug.{DebugCustomXbar, DebugIO, DebugTransportModuleJTAG, JtagDTMConfig, PSDIO, ResetCtrlIO, SystemJTAGIO, TLDebugModule} 34import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode 35import freechips.rocketchip.devices.debug._ 36 37// this file uses code from rocketchip Periphery.scala 38// to simplify the code we remove options for apb, cjtag and dmi 39// this module creates wrapped dm and dtm 40 41// TODO 42// 1 cannot write csrs using gdb ? 43// 2 Memory reads (0) on gdb connection ? 44// 3 Trigger Stuff 45 46class DebugModule(numCores: Int)(implicit p: Parameters) extends LazyModule { 47 48 val debug = LazyModule(new TLDebugModule(8)(p)) 49 50// debug.node := TLFragmenter() := peripheralXbar 51 val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false))) 52 debug.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node 53 54// debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 55// l2xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node 56// } 57 val fakeTreeNode = new GenericLogicalTreeNode 58 LogicalModuleTree.add(fakeTreeNode, debug.logicalTreeNode) 59 60 lazy val module = new LazyRawModuleImp(this) { 61 val io = IO(new Bundle{ 62 val resetCtrl = new ResetCtrlIO(numCores)(p) 63 val debugIO = new DebugIO()(p) 64 val clock = Input(Bool()) 65 val reset = Input(Bool()) 66 }) 67 debug.module.io.tl_reset := io.reset // this should be TL reset 68 debug.module.io.tl_clock := io.clock.asClock // this should be TL clock 69 debug.module.io.hartIsInReset := io.resetCtrl.hartIsInReset 70 io.resetCtrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }} 71 72 io.debugIO.clockeddmi.foreach { dbg => debug.module.io.dmi.get <> dbg } // not connected in current case since we use dtm 73 debug.module.io.debug_reset := io.debugIO.reset 74 debug.module.io.debug_clock := io.debugIO.clock 75 io.debugIO.ndreset := debug.module.io.ctrl.ndreset 76 io.debugIO.dmactive := debug.module.io.ctrl.dmactive 77 debug.module.io.ctrl.dmactiveAck := io.debugIO.dmactiveAck 78 io.debugIO.extTrigger.foreach { x => debug.module.io.extTrigger.foreach {y => x <> y}} 79 debug.module.io.ctrl.debugUnavail.foreach { _ := false.B } 80 81 val dtm = io.debugIO.systemjtag.map(instantiateJtagDTM(_)) 82 83 def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = { 84 val c = new JtagDTMKeyDefault 85 val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, c)) 86 dtm.io.jtag <> sj.jtag 87 88 io.debugIO.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS | x } // force TMS high when debug is disabled 89 90 dtm.io.jtag_clock := sj.jtag.TCK 91 dtm.io.jtag_reset := sj.reset 92 dtm.io.jtag_mfr_id := sj.mfr_id 93 dtm.io.jtag_part_number := sj.part_number 94 dtm.io.jtag_version := sj.version 95 dtm.rf_reset := sj.reset 96 debug.module.io.dmi.get.dmi <> dtm.io.dmi 97 debug.module.io.dmi.get.dmiClock := sj.jtag.TCK 98 debug.module.io.dmi.get.dmiReset := sj.reset 99 dtm 100 } 101 } 102} 103 104object XSDebugModuleParams { 105 106 def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = { 107 new DebugModuleParams().copy( 108 nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), 109 maxSupportedSBAccess = xlen, 110 hasBusMaster = true, 111 baseAddress = BigInt(0x38020000), 112 nScratch = 2 113 ) 114 } 115} 116 117case object EnableJtag extends Field[Bool] 118 119class SimJTAG(tickDelay: Int = 50)(implicit val p: Parameters) extends ExtModule(Map("TICK_DELAY" -> IntParam(tickDelay))) 120 with HasExtModuleResource { 121 122 val clock = IO(Input(Clock())) 123 val reset = IO(Input(Bool())) 124 val jtag = IO(new JTAGIO(hasTRSTn = true)) 125 val enable = IO(Input(Bool())) 126 val init_done = IO(Input(Bool())) 127 val exit = IO(Output(UInt(32.W))) 128 129 def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, done: Bool, tbsuccess: Bool) = { 130 dutio.TCK := jtag.TCK 131 dutio.TMS := jtag.TMS 132 dutio.TDI := jtag.TDI 133 jtag.TDO := dutio.TDO 134 135 clock := tbclock 136 reset := tbreset 137 138 enable := p(EnableJtag) 139 init_done := done 140 141 // Success is determined by the gdbserver 142 // which is controlling this simulation. 143 tbsuccess := exit === 1.U 144 when (exit >= 2.U) { 145 printf("*** FAILED *** (exit code = %d)\n", exit >> 1.U) 146 stop(1) 147 } 148 } 149} 150