1package device 2 3import chisel3._ 4import chisel3.util._ 5 6import bus.axi4._ 7import utils._ 8 9class AXI4UART extends AXI4SlaveModule(new AXI4Lite) { 10 val rxfifo = RegInit(0.U(32.W)) 11 val txfifo = Reg(UInt(32.W)) 12 val stat = RegInit(1.U(32.W)) 13 val ctrl = RegInit(0.U(32.W)) 14 15 def putc(c: UInt): UInt = { printf("%c", c(7,0)); c } 16 17 val mapping = Map( 18 RegMap(0x0, rxfifo), 19 RegMap(0x4, txfifo, putc), 20 RegMap(0x8, stat), 21 RegMap(0xc, ctrl) 22 ) 23 24 RegMap.generate(mapping, raddr(3,0), in.r.bits.data, 25 waddr(3,0), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb)) 26} 27