xref: /XiangShan/src/main/scala/device/AXI4UART.scala (revision d18aeea69faedce0e5925dcce26c667312a50967) 
1package device
2
3import chisel3._
4import chisel3.util._
5
6import bus.axi4._
7import utils._
8
9class UARTGetc extends BlackBox with HasBlackBoxInline {
10  val io = IO(new Bundle {
11    val clk = Input(Clock())
12    val getc = Input(Bool())
13    val ch = Output(UInt(8.W))
14  })
15
16  setInline("UARTGetc.v",
17    s"""
18      |import "DPI-C" function void uart_getc(output byte ch);
19      |
20      |module UARTGetc (
21      |  input clk,
22      |  input getc,
23      |  output reg [7:0] ch
24      |);
25      |
26      |  always@(posedge clk) begin
27      |    if (getc) uart_getc(ch);
28      |  end
29      |
30      |endmodule
31     """.stripMargin)
32}
33
34class UARTPutc extends BlackBox with HasBlackBoxInline {
35  val io = IO(new Bundle {
36    val clk = Input(Clock())
37    val putc = Input(Bool())
38    val ch = Input(UInt(8.W))
39  })
40
41  setInline("UARTPutc.v",
42    """
43       |module UARTPutc (
44       |  input clk,
45       |  input putc,
46       |  input [7:0] ch
47       |);
48       |
49       |  always@(posedge clk) begin
50       |    if (putc) begin
51       |      $fwrite(32'h80000001, "%c", ch);
52       |    end
53       |  end
54       |
55       |endmodule
56     """.stripMargin)
57}
58
59class AXI4UART extends AXI4SlaveModule(new AXI4Lite) {
60  val rxfifo = RegInit(0.U(32.W))
61  val txfifo = Reg(UInt(32.W))
62  val stat = RegInit(1.U(32.W))
63  val ctrl = RegInit(0.U(32.W))
64
65  val getcHelper = Module(new UARTGetc)
66  getcHelper.io.clk := clock
67  getcHelper.io.getc := (raddr(3,0) === 0.U && ren)
68
69  val putcHelper = Module(new UARTPutc)
70  putcHelper.io.clk := clock
71  putcHelper.io.putc := waddr(3, 0)===4.U && in.w.fire()
72  putcHelper.io.ch := in.w.bits.data(7, 0)
73
74//  def putc(c: UInt): UInt = { printf("%c", c(7,0)); c }
75  def getc = getcHelper.io.ch
76
77  val mapping = Map(
78    RegMap(0x0, getc, RegMap.Unwritable),
79    RegMap(0x4, txfifo),
80    RegMap(0x8, stat),
81    RegMap(0xc, ctrl)
82  )
83
84  RegMap.generate(mapping, raddr(3,0), in.r.bits.data,
85    waddr(3,0), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb >> waddr(2,0)))
86}
87