1package device 2 3import chisel3._ 4import chisel3.util._ 5 6import bus.axi4._ 7import utils._ 8 9class UARTIO extends Bundle { 10 val out = new Bundle { 11 val valid = Output(Bool()) 12 val ch = Output(UInt(8.W)) 13 } 14 val in = new Bundle { 15 val valid = Output(Bool()) 16 val ch = Input(UInt(8.W)) 17 } 18} 19 20class AXI4UART extends AXI4SlaveModule(new AXI4Lite, new UARTIO) { 21 val rxfifo = RegInit(0.U(32.W)) 22 val txfifo = Reg(UInt(32.W)) 23 val stat = RegInit(1.U(32.W)) 24 val ctrl = RegInit(0.U(32.W)) 25 26 io.extra.get.out.valid := (waddr(3,0) === 4.U && in.w.fire()) 27 io.extra.get.out.ch := in.w.bits.data(7,0) 28 io.extra.get.in.valid := (raddr(3,0) === 0.U && ren) 29 30 val mapping = Map( 31 RegMap(0x0, io.extra.get.in.ch, RegMap.Unwritable), 32 RegMap(0x4, txfifo), 33 RegMap(0x8, stat), 34 RegMap(0xc, ctrl) 35 ) 36 37 RegMap.generate(mapping, raddr(3,0), in.r.bits.data, 38 waddr(3,0), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb >> waddr(2,0))) 39} 40