xref: /XiangShan/src/main/scala/device/AXI4UART.scala (revision 8171fe6a7aec901e95ab6e27d96c0bf3a399ebe9) 
1package device
2
3import chisel3._
4import chisel3.util._
5
6import bus.axi4._
7import utils._
8
9class UARTGetc extends BlackBox with HasBlackBoxInline {
10  val io = IO(new Bundle {
11    val clk = Input(Clock())
12    val getc = Input(Bool())
13    val ch = Output(UInt(8.W))
14  })
15
16  setInline("UARTGetc.v",
17    s"""
18      |import "DPI-C" function byte uart_getc(output byte ch);
19      |
20      |module UARTGetc (
21      |  input clk,
22      |  input getc,
23      |  output reg [7:0] ch
24      |);
25      |
26      |  always@(posedge clk) begin
27      |    if (getc) uart_getc(ch);
28      |  end
29      |
30      |endmodule
31     """.stripMargin)
32}
33
34class AXI4UART extends AXI4SlaveModule(new AXI4Lite) {
35  val rxfifo = RegInit(0.U(32.W))
36  val txfifo = Reg(UInt(32.W))
37  val stat = RegInit(1.U(32.W))
38  val ctrl = RegInit(0.U(32.W))
39
40  val getcHelper = Module(new UARTGetc)
41  getcHelper.io.clk := clock
42  getcHelper.io.getc := (raddr(3,0) === 0.U && ren)
43
44  def putc(c: UInt): UInt = { printf("%c", c(7,0)); c }
45  def getc = getcHelper.io.ch
46
47  val mapping = Map(
48    RegMap(0x0, getc, RegMap.Unwritable),
49    RegMap(0x4, txfifo, putc),
50    RegMap(0x8, stat),
51    RegMap(0xc, ctrl)
52  )
53
54  RegMap.generate(mapping, raddr(3,0), in.r.bits.data,
55    waddr(3,0), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb))
56}
57