xref: /XiangShan/src/main/scala/device/AXI4Timer.scala (revision 66314a3840e5ebe6cc81ca4725bde95942f67489) 
1package device
2
3import chisel3._
4import chisel3.util._
5import chisel3.util.experimental.BoringUtils
6import bus.axi4._
7import utils._
8
9class TimerIO extends Bundle {
10  val mtip = Output(Bool())
11}
12
13class AXI4Timer(sim: Boolean = false) extends AXI4SlaveModule(new AXI4Lite, new TimerIO) {
14  val mtime = RegInit(0.U(64.W))  // unit: us
15  val mtimecmp = RegInit(0.U(64.W))
16
17  val clk = (if (!sim) 40 /* 40MHz / 1000000 */ else 10000)
18  val freq = RegInit(clk.U(16.W))
19  val inc = RegInit(1000.U(16.W))
20
21  val cnt = RegInit(0.U(16.W))
22  val nextCnt = cnt + 1.U
23  cnt := Mux(nextCnt < freq, nextCnt, 0.U)
24  val tick = (nextCnt === freq)
25  when (tick) { mtime := mtime + inc }
26
27  if (sim) {
28    val isWFI = WireInit(false.B)
29    BoringUtils.addSink(isWFI, "isWFI")
30    when (isWFI) { mtime := mtime + 100000.U }
31  }
32
33  val mapping = Map(
34    RegMap(0x4000, mtimecmp),
35    RegMap(0x8000, freq),
36    RegMap(0x8008, inc),
37    RegMap(0xbff8, mtime)
38  )
39  def getOffset(addr: UInt) = addr(15,0)
40
41  RegMap.generate(mapping, getOffset(raddr), in.r.bits.data,
42    getOffset(waddr), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb))
43
44  io.extra.get.mtip := RegNext(mtime >= mtimecmp)
45}
46