1package device 2 3import chisel3._ 4import chisel3.util._ 5 6import bus.axi4._ 7import utils._ 8 9class KeyboardIO extends Bundle { 10 val ps2Clk = Input(Bool()) 11 val ps2Data = Input(Bool()) 12} 13 14// this Module is not tested 15class AXI4Keyboard extends AXI4SlaveModule(new AXI4Lite, new KeyboardIO) { 16 val buf = Reg(UInt(10.W)) 17 val ps2ClkLatch = RegNext(io.extra.get.ps2Clk) 18 val negedge = RegNext(ps2ClkLatch) && ~ps2ClkLatch 19 when (negedge) { buf := Cat(io.extra.get.ps2Data, buf(9,1)) } 20 21 val cnt = Counter(negedge, 10) 22 val queue = Module(new Queue(UInt(8.W), 8)) 23 queue.io.enq.valid := cnt._2 && !buf(0) && io.extra.get.ps2Data && buf(9,1).xorR 24 queue.io.enq.bits := buf(8,1) 25 queue.io.deq.ready := in.r.ready 26 27 in.r.bits.data := Mux(queue.io.deq.valid, queue.io.deq.bits, 0.U) 28} 29