1package device 2 3import chisel3._ 4import chisel3.util._ 5import chipsalliance.rocketchip.config.Parameters 6import freechips.rocketchip.diplomacy.AddressSet 7import utils._ 8 9class KeyboardIO extends Bundle { 10 val ps2Clk = Input(Bool()) 11 val ps2Data = Input(Bool()) 12} 13 14// this Module is not tested 15class AXI4Keyboard 16( 17 address: AddressSet 18)(implicit p: Parameters) 19 extends AXI4SlaveModule(address, executable = false, _extra = new KeyboardIO) 20{ 21 override lazy val module = new AXI4SlaveModuleImp[KeyboardIO](this){ 22 val buf = Reg(UInt(10.W)) 23 val ps2ClkLatch = RegNext(io.extra.get.ps2Clk) 24 val negedge = RegNext(ps2ClkLatch) && ~ps2ClkLatch 25 when (negedge) { buf := Cat(io.extra.get.ps2Data, buf(9,1)) } 26 27 val cnt = Counter(negedge, 10) 28 val queue = Module(new Queue(UInt(8.W), 8)) 29 queue.io.enq.valid := cnt._2 && !buf(0) && io.extra.get.ps2Data && buf(9,1).xorR 30 queue.io.enq.bits := buf(8,1) 31 queue.io.deq.ready := in.r.ready 32 33 in.r.bits.data := Mux(queue.io.deq.valid, queue.io.deq.bits, 0.U) 34 } 35 36} 37