xref: /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala (revision 964c1fbcf46544f07d70f9b5daafa9313934e9f4) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
22import freechips.rocketchip.diplomacy.AddressSet
23import utils._
24
25// we support 256 interrupt bits by default
26class IntrGenIO extends Bundle {
27  val intrVec = Output(UInt(64.W))
28}
29
30class AXI4IntrGenerator
31(
32  address: Seq[AddressSet]
33)(implicit p: Parameters)
34  extends AXI4SlaveModule(address, executable = false, _extra = new IntrGenIO)
35{
36
37  override lazy val module = new AXI4SlaveModuleImp(this){
38
39    val intrGenRegs = RegInit(VecInit(Seq.fill(8)(0.U(32.W))))
40
41    // 0x0 - 0x8
42    val intrReg = VecInit(intrGenRegs.take(2))
43    // 0x8 - 0x10
44    val randEnable = VecInit(intrGenRegs.slice(2, 4))
45    // 0x10
46    val randMask = intrGenRegs(4)
47    val randCounter = intrGenRegs(5)
48    val randThres = intrGenRegs(6)
49
50    val randomPosition = LFSR64()(5, 0)
51    val randomCondition = randCounter === randThres && randEnable(randomPosition(5))(randomPosition(4, 0))
52    randCounter := randCounter + 1.U
53    when (randomCondition) {
54      intrGenRegs(randomPosition(5)) := intrReg(randomPosition(5)) | UIntToOH(randomPosition(4, 0))
55    }
56
57    io.extra.get.intrVec := Cat(intrReg.reverse)
58
59    // Delay the intr gen for 1000 cycles.
60    val delayCycles = 1000
61    var w_fire = in.w.fire && in.w.bits.data =/= 0.U
62    for (i <- 0 until delayCycles) {
63      w_fire = RegNext(w_fire, init=false.B)
64    }
65    val w_data = DelayN(in.w.bits.data(31, 0), delayCycles)
66    when (w_fire) {
67      intrGenRegs(DelayN(waddr(4, 2), delayCycles)) := w_data
68    }
69    // Clear takes effect immediately
70    when (in.w.fire && in.w.bits.data === 0.U) {
71      intrGenRegs(waddr(4, 2)) := 0.U
72    }
73    // write resets the threshold and counter
74    when (in.w.fire && in.w.bits.data === 0.U || w_fire) {
75      randThres := LFSR64() & randMask
76      randCounter := 0.U
77    }
78
79    in.r.bits.data := intrReg(raddr)
80  }
81}
82