1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package device 18 19import chisel3._ 20import chisel3.util._ 21import chipsalliance.rocketchip.config.Parameters 22import freechips.rocketchip.diplomacy.AddressSet 23import utils._ 24 25// we support 256 interrupt bits by default 26class IntrGenIO extends Bundle { 27 val intrVec = Output(UInt(256.W)) 28} 29 30class AXI4IntrGenerator 31( 32 address: Seq[AddressSet] 33)(implicit p: Parameters) 34 extends AXI4SlaveModule(address, executable = false, _extra = new IntrGenIO) 35{ 36 37 override lazy val module = new AXI4SlaveModuleImp(this){ 38 39 val intrReg = RegInit(VecInit(Seq.fill(8)(0.U(32.W)))) 40 io.extra.get.intrVec := Cat(intrReg.reverse) 41 42 when (in.w.fire()) { 43 intrReg(waddr(4, 2)) := in.w.bits.data(31, 0) 44 } 45 46 in.r.bits.data := intrReg(raddr) 47 } 48} 49