1c6d43980SLemover/*************************************************************************************** 2c6d43980SLemover* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3f320e0f0SYinan Xu* Copyright (c) 2020-2021 Peng Cheng Laboratory 4c6d43980SLemover* 5c6d43980SLemover* XiangShan is licensed under Mulan PSL v2. 6c6d43980SLemover* You can use this software according to the terms and conditions of the Mulan PSL v2. 7c6d43980SLemover* You may obtain a copy of Mulan PSL v2 at: 8c6d43980SLemover* http://license.coscl.org.cn/MulanPSL2 9c6d43980SLemover* 10c6d43980SLemover* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11c6d43980SLemover* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12c6d43980SLemover* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13c6d43980SLemover* 14c6d43980SLemover* See the Mulan PSL v2 for more details. 15c6d43980SLemover***************************************************************************************/ 16c6d43980SLemover 17b6a21a24SYinan Xupackage device 18b6a21a24SYinan Xu 19b6a21a24SYinan Xuimport chisel3._ 20b6a21a24SYinan Xuimport chisel3.util._ 21b6a21a24SYinan Xuimport chipsalliance.rocketchip.config.Parameters 22b6a21a24SYinan Xuimport freechips.rocketchip.diplomacy.AddressSet 23b6a21a24SYinan Xuimport utils._ 24b6a21a24SYinan Xu 25b6a21a24SYinan Xu// we support 256 interrupt bits by default 26b6a21a24SYinan Xuclass IntrGenIO extends Bundle { 27*151b6d60SYinan Xu val intrVec = Output(UInt(64.W)) 28b6a21a24SYinan Xu} 29b6a21a24SYinan Xu 30b6a21a24SYinan Xuclass AXI4IntrGenerator 31b6a21a24SYinan Xu( 32b6a21a24SYinan Xu address: Seq[AddressSet] 33b6a21a24SYinan Xu)(implicit p: Parameters) 34b6a21a24SYinan Xu extends AXI4SlaveModule(address, executable = false, _extra = new IntrGenIO) 35b6a21a24SYinan Xu{ 36b6a21a24SYinan Xu 37b6a21a24SYinan Xu override lazy val module = new AXI4SlaveModuleImp(this){ 38b6a21a24SYinan Xu 39*151b6d60SYinan Xu val intrGenRegs = RegInit(VecInit(Seq.fill(8)(0.U(32.W)))) 40*151b6d60SYinan Xu 41*151b6d60SYinan Xu // 0x0 - 0x8 42*151b6d60SYinan Xu val intrReg = VecInit(intrGenRegs.take(2)) 43*151b6d60SYinan Xu // 0x8 - 0x10 44*151b6d60SYinan Xu val randEnable = VecInit(intrGenRegs.slice(2, 4)) 45*151b6d60SYinan Xu // 0x10 46*151b6d60SYinan Xu val randMask = intrGenRegs(4) 47*151b6d60SYinan Xu val randCounter = intrGenRegs(5) 48*151b6d60SYinan Xu val randThres = intrGenRegs(6) 49*151b6d60SYinan Xu 50*151b6d60SYinan Xu val randomPosition = LFSR64()(5, 0) 51*151b6d60SYinan Xu val randomCondition = randCounter === randThres && randEnable(randomPosition(5))(randomPosition(4, 0)) 52*151b6d60SYinan Xu randCounter := randCounter + 1.U 53*151b6d60SYinan Xu when (randomCondition) { 54*151b6d60SYinan Xu intrGenRegs(randomPosition(5)) := intrReg(randomPosition(5)) | UIntToOH(randomPosition(4, 0)) 55*151b6d60SYinan Xu } 56*151b6d60SYinan Xu 57b6a21a24SYinan Xu io.extra.get.intrVec := Cat(intrReg.reverse) 58b6a21a24SYinan Xu 59*151b6d60SYinan Xu when (in.w.fire) { 60*151b6d60SYinan Xu randThres := LFSR64() & randMask 61*151b6d60SYinan Xu intrGenRegs(waddr(4, 2)) := in.w.bits.data(31, 0) 62*151b6d60SYinan Xu randCounter := 0.U 63b6a21a24SYinan Xu } 64b6a21a24SYinan Xu 65b6a21a24SYinan Xu in.r.bits.data := intrReg(raddr) 66b6a21a24SYinan Xu } 67b6a21a24SYinan Xu} 68