/linux-6.14.4/Documentation/ABI/stable/ |
D | sysfs-driver-firmware-zynqmp | 1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs* 11 The register is reset during system or power-on 17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs* 38 This register is only reset by the power-on reset 46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/firmware/xilinx/ |
D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx firmware driver 10 - Nava kishore Manne <[email protected]> 12 description: The zynqmp-firmware node describes the interface to platform 13 firmware. ZynqMP has an interface to communicate with secure firmware. 14 Firmware driver provides an interface to firmware APIs. Interface APIs 23 - description: For implementations complying for Zynq Ultrascale+ MPSoC. [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/crypto/ |
D | xlnx,zynqmp-aes.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator 10 - Kalyani Akula <[email protected]> 11 - Michal Simek <[email protected]> 14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to 19 const: xlnx,zynqmp-aes 22 - compatible [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/power/reset/ |
D | xlnx,zynqmp-power.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michal Simek <[email protected]> 13 The zynqmp-power node describes the power management configurations. 18 const: xlnx,zynqmp-power 28 that will be the phandle to the intended sub-mailbox 34 xlnx,zynqmp-ipi-mailbox.txt for typical controller that 37 - description: tx channel [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/fpga/ |
D | xlnx,zynqmp-pcap-fpga.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Nava kishore Manne <[email protected]> 14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to 16 firmware interface. 20 const: xlnx,zynqmp-pcap-fpga 23 - compatible 28 - | [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/clock/ |
D | xlnx,versal-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michal Simek <[email protected]> 20 - enum: 21 - xlnx,versal-clk 22 - xlnx,zynqmp-clk 23 - items: 24 - enum: [all …]
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/linux-6.14.4/drivers/firmware/xilinx/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 4 menu "Zynq MPSoC Firmware Drivers" 8 bool "Enable Xilinx Zynq MPSoC firmware interface" 13 Firmware interface driver is used by different 14 drivers to communicate with the firmware for 16 Say yes to enable ZynqMP firmware interface driver. 20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs" 23 Say yes to enable ZynqMP firmware interface debug APIs.
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D | zynqmp-debug.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Xilinx Zynq MPSoC Firmware layer for debugfs APIs 5 * Copyright (C) 2014-2018 Xilinx, Inc. 19 #include <linux/firmware/xlnx-zynqmp.h> 20 #include "zynqmp-debug.h" 62 * zynqmp_pm_ioctl - PM IOCTL for device control and configs 79 * zynqmp_pm_argument_value() - Extract argument value from a PM-API request 80 * @arg: Entered PM-API argument in string format 99 * get_pm_api_id() - Extract API-ID from a PM-API request 100 * @pm_api_req: Entered PM-API argument in string format [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/gpio/ |
D | xlnx,zynqmp-gpio-modepin.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ZynqMP Mode Pin GPIO controller 10 PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin 15 - Mubin Sayyed <[email protected]> 16 - Radhey Shyam Pandey <[email protected]> 20 const: xlnx,zynqmp-gpio-modepin 22 gpio-controller: true [all …]
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/linux-6.14.4/Documentation/driver-api/xilinx/ |
D | eemi.rst | 5 Xilinx Zynq MPSoC Firmware Interface 6 ------------------------------------- 7 The zynqmp-firmware node describes the interface to platform firmware. 8 ZynqMP has an interface to communicate with secure firmware. Firmware 9 driver provides an interface to firmware APIs. Interface APIs can be 13 ---------------------------------------------- 23 ------ 30 - IOCTL_SET_PLL_FRAC_MODE 8 31 - IOCTL_GET_PLL_FRAC_MODE 9 32 - IOCTL_SET_PLL_FRAC_DATA 10 [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/remoteproc/ |
D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ben Levinsky <[email protected]> 11 - Tanmay Shah <[email protected]> 14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for 15 real-time processing based on the Cortex-R5F processor core from ARM. 16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a 17 floating-point unit that implements the Arm VFPv3 instruction set. [all …]
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/linux-6.14.4/drivers/clk/zynqmp/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 4 bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers" 8 Support for the Zynqmp Ultrascale clock controller. 9 It has a dependency on the PMU firmware.
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/linux-6.14.4/drivers/fpga/ |
D | zynqmp-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <linux/dma-mapping.h> 7 #include <linux/fpga/fpga-mgr.h> 13 #include <linux/firmware/xlnx-zynqmp.h> 19 * struct zynqmp_fpga_priv - Private data structure 34 priv = mgr->priv; in zynqmp_fpga_ops_write_init() 35 priv->flags = info->flags; in zynqmp_fpga_ops_write_init() 49 priv = mgr->priv; in zynqmp_fpga_ops_write() 51 kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); in zynqmp_fpga_ops_write() 53 return -ENOMEM; in zynqmp_fpga_ops_write() [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/mailbox/ |
D | xlnx,zynqmp-ipi-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 +-------------------------------------+ 15 | Xilinx ZynqMP IPI Controller | 16 +-------------------------------------+ 17 +--------------------------------------------------+ 18 TF-A | | 21 +--------------------------+ | [all …]
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/linux-6.14.4/arch/arm64/boot/dts/xilinx/ |
D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/interrupt-controller/arm-gic.h> 18 #include <dt-bindings/interrupt-controller/irq.h> 19 #include <dt-bindings/power/xlnx-zynqmp-power.h> 20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 21 #include <dt-bindings/thermal/thermal.h> [all …]
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/linux-6.14.4/drivers/crypto/xilinx/ |
D | zynqmp-sha.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Xilinx ZynqMP SHA Driver. 12 #include <linux/dma-mapping.h> 13 #include <linux/firmware/xlnx-zynqmp.h> 55 tfm_ctx->dev = drv_ctx->dev; in zynqmp_sha_init_tfm() 63 tfm_ctx->fbk_tfm = fallback_tfm; in zynqmp_sha_init_tfm() 64 hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm); in zynqmp_sha_init_tfm() 73 if (tfm_ctx->fbk_tfm) { in zynqmp_sha_exit_tfm() 74 crypto_free_shash(tfm_ctx->fbk_tfm); in zynqmp_sha_exit_tfm() 75 tfm_ctx->fbk_tfm = NULL; in zynqmp_sha_exit_tfm() [all …]
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D | zynqmp-aes-gcm.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Xilinx ZynqMP AES Driver. 12 #include <linux/dma-mapping.h> 14 #include <linux/firmware/xlnx-zynqmp.h> 82 struct device *dev = tfm_ctx->dev; in zynqmp_aes_aead_cipher() 92 if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY) in zynqmp_aes_aead_cipher() 93 dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE in zynqmp_aes_aead_cipher() 96 dma_size = req->cryptlen + GCM_AES_IV_SIZE; in zynqmp_aes_aead_cipher() 100 return -ENOMEM; in zynqmp_aes_aead_cipher() 106 return -ENOMEM; in zynqmp_aes_aead_cipher() [all …]
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/linux-6.14.4/drivers/nvmem/ |
D | zynqmp_nvmem.c | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. 7 #include <linux/dma-mapping.h> 9 #include <linux/nvmem-provider.h> 12 #include <linux/firmware/xlnx-zynqmp.h> 40 * struct xilinx_efuse - the basic structure 44 * @flag: 0 - represents efuse read and 1- represents efuse write 45 * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write 46 * 1 - represents puf user fuse row number. 74 return -EOPNOTSUPP; in zynqmp_efuse_access() [all …]
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/linux-6.14.4/drivers/pinctrl/ |
D | pinctrl-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * ZynqMP pin controller 11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 20 #include <linux/firmware/xlnx-zynqmp.h> 22 #include <linux/pinctrl/pinconf-generic.h> 28 #include "pinctrl-utils.h" 55 * struct zynqmp_pmux_function - a pinmux function 70 * struct zynqmp_pinctrl - driver data 90 * struct zynqmp_pctrl_group - Pin control group info 109 return pctrl->ngroups + zynqmp_desc.npins; in zynqmp_pctrl_get_groups_count() [all …]
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/linux-6.14.4/drivers/remoteproc/ |
D | xlnx_r5_remoteproc.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * ZynqMP R5 Remote Processor driver 7 #include <dt-bindings/power/xlnx-zynqmp-power.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/firmware/xlnx-zynqmp.h> 12 #include <linux/mailbox/zynqmp-ipi-message.h> 34 * reflects possible values of xlnx,cluster-mode dt-property 38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */ 43 * struct mem_bank_data - Memory Bank description 48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/ |
D | xlnx,zynqmp-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx ZynqMP Pinctrl 10 - Sai Krishna Potthuri <[email protected]> 13 Please refer to pinctrl-bindings.txt in this directory for details of the 17 ZynqMP's pin configuration nodes act as a container for an arbitrary number of 21 parameters, such as pull-up, slew rate, etc. 31 const: xlnx,zynqmp-pinctrl [all …]
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/linux-6.14.4/drivers/pmdomain/xilinx/ |
D | zynqmp-pm-domains.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * ZynqMP Generic PM domain support 5 * Copyright (C) 2015-2019 Xilinx, Inc. 20 #include <linux/firmware/xlnx-zynqmp.h> 27 * struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain 42 * zynqmp_gpd_is_active_wakeup_path() - Check if device is in wakeup source 65 * zynqmp_gpd_power_on() - Power on PM domain 78 ret = zynqmp_pm_set_requirement(pd->node_id, in zynqmp_gpd_power_on() 83 dev_err(&domain->dev, in zynqmp_gpd_power_on() 85 ZYNQMP_PM_CAPABILITY_ACCESS, pd->node_id, ret); in zynqmp_gpd_power_on() [all …]
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/linux-6.14.4/drivers/gpio/ |
D | gpio-zynqmp-modepin.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Driver for the ps-mode pin configuration. 16 #include <linux/firmware/xlnx-zynqmp.h> 18 /* 4-bit boot mode pins */ 22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device 28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured 50 * modepin_gpio_set_value - Modify the state of the pin with specified value 83 * modepin_gpio_dir_in - Set the direction of the specified GPIO pin as input 95 * modepin_gpio_dir_out - Set the direction of the specified GPIO pin as output 109 * modepin_gpio_probe - Initialization method for modepin_gpio [all …]
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/linux-6.14.4/drivers/reset/ |
D | reset-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0+ 10 #include <linux/reset-controller.h> 11 #include <linux/firmware/xlnx-zynqmp.h> 13 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START) 39 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_assert() 48 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_deassert() 59 err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val); in zynqmp_reset_status() 71 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_reset() 78 return reset_spec->args[0]; in zynqmp_reset_of_xlate() 107 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in zynqmp_reset_probe() [all …]
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D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 12 via GPIOs or SoC-internal reset controller modules. 87 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 90 If compiled as module, it will be called reset-gpio. 132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 204 tristate "Raspberry Pi 4 Firmware Reset Driver" 208 Raspberry Pi 4's co-processor controls some of the board's HW 211 interfacing with RPi4's co-processor and model these firmware 227 controlled by firmware that implements the SCMI interface. 230 firmware controlling all the reset signals. [all …]
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