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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
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/linux-6.14.4/drivers/media/tuners/
Dmt2060.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 { .addr = priv->cfg->i2c_address, .flags = 0, .len = 1 }, in mt2060_readreg()
32 { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .len = 1 }, in mt2060_readreg()
39 return -ENOMEM; in mt2060_readreg()
47 if (i2c_transfer(priv->i2c, msg, 2) != 2) { in mt2060_readreg()
49 rc = -EREMOTEIO; in mt2060_readreg()
61 .addr = priv->cfg->i2c_address, .flags = 0, .len = 2 in mt2060_writereg()
68 return -ENOMEM; in mt2060_writereg()
75 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in mt2060_writereg()
77 rc = -EREMOTEIO; in mt2060_writereg()
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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
45 * Display PLLs used for driving outputs vary by platform. While some have
46 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
48 * share a PLL if their configurations match.
51 * intel_shared_dpll_init() initializes the PLLs for the given platform. The
52 * users of a PLL are tracked and that tracking is integrated with the atomic
62 /* platform specific hooks for managing DPLLs */
65 * Hook for enabling the pll, called from intel_enable_shared_dpll() if
66 * the pll is not already enabled.
69 struct intel_shared_dpll *pll,
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/linux-6.14.4/drivers/clk/ti/
Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
183 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
184 "clock-output-names", in ti_adpll_clk_get_name()
190 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
191 d->pa, postfix); in ti_adpll_clk_get_name()
207 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
208 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
214 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
216 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1); in ti_adpll_setup_clock()
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/linux-6.14.4/drivers/video/fbdev/
Dcyber2000fb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1998-2002 Russell King
49 #include <linux/i2c-algo-bit.h>
52 #include <asm/mach-types.h>
109 #define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg))
110 #define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg))
111 #define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg))
113 #define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg))
149 /* -------------------- Hardware specific routines ------------------------- */
160 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { in cyber2000fb_fillrect()
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/linux-6.14.4/drivers/iio/frequency/
Dadf4350.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
22 #include <linux/clk-provider.h>
83 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { in adf4350_sync_config()
84 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
93 st->val = cpu_to_be32(st->regs[i] | i); in adf4350_sync_config()
94 ret = spi_write(st->spi, &st->val, 4); in adf4350_sync_config()
97 st->regs_hw[i] = st->regs[i]; in adf4350_sync_config()
98 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", in adf4350_sync_config()
99 i, (u32)st->regs[i] | i); in adf4350_sync_config()
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