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/linux-6.14.4/Documentation/devicetree/bindings/gpu/host1x/
Dnvidia,tegra234-nvdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <[email protected]>
16 - Mikko Perttunen <[email protected]>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra234-nvdec
32 clock-names:
34 - const: nvdec
[all …]
/linux-6.14.4/Documentation/firmware-guide/acpi/
Dchromeos-acpi-device.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Chrome OS ACPI Device
7 Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
8 The plug and play ID of a Chrome OS ACPI device is GGL0001 and the hardware ID is
11 .. flat-table:: Supported ACPI Objects
13 :header-rows: 1
15 * - Object
16 - Description
18 * - CHSW
19 - Chrome OS switch positions
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/linux-6.14.4/drivers/gpu/drm/tegra/
Driscv.c1 // SPDX-License-Identifier: GPL-2.0-only
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors() local
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
51 READ_PROP("nvidia,bl-manifest-offset", &bl->manifest_offset); in tegra_drm_riscv_read_descriptors()
52 READ_PROP("nvidia,bl-code-offset", &bl->code_offset); in tegra_drm_riscv_read_descriptors()
53 READ_PROP("nvidia,bl-data-offset", &bl->data_offset); in tegra_drm_riscv_read_descriptors()
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Dfalcon.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
20 static void falcon_writel(struct falcon *falcon, u32 value, u32 offset) in falcon_writel() argument
22 writel(value, falcon->regs + offset); in falcon_writel()
29 return readl_poll_timeout(falcon->regs + FALCON_IDLESTATE, value, in falcon_wait_idle()
37 return readl_poll_timeout(falcon->regs + FALCON_DMATRFCMD, value, in falcon_dma_wait_idle()
43 unsigned long offset, in falcon_copy_chunk() argument
59 falcon_writel(falcon, offset, FALCON_DMATRFMOFFS); in falcon_copy_chunk()
69 u32 *virt = falcon->firmware.virt; in falcon_copy_firmware_image()
73 for (i = 0; i < firmware->size / sizeof(u32); i++) in falcon_copy_firmware_image()
[all …]
/linux-6.14.4/drivers/tee/optee/
Doptee_ffa.h1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2019-2021, 2023 Linaro Limited
7 * This file is exported by OP-TEE and is kept in sync between secure world
8 * and normal world drivers. We're using ARM FF-A 1.0 specification.
23 * defined in FF-A specification:
27 * w3-w7: Implementation defined, free to be used below
38 * Returns the API version implemented, currently follows the FF-A version.
41 * w4-w7: Not used (MBZ)
46 * w5-w7: Not used (MBZ)
51 * Returns the revision of OP-TEE.
[all …]
Doptee_smc.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2021, Linaro Limited
8 #include <linux/arm-smccc.h>
28 * Normal cached memory (write-back), shareable for SMP systems and not
36 * 32-bit registers.
44 * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b.
73 * Get UUID of Trusted OS.
75 * Used by non-secure world to figure out which Trusted OS is installed.
76 * Note that returned UUID is the UUID of the Trusted OS, not of the API.
78 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
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/linux-6.14.4/Documentation/livepatch/
Dmodule-elf-format.rst16 Formerly, livepatch required separate architecture-specific code to write
17 relocations. However, arch-specific code to write relocations already
19 code. So, instead of duplicating code and re-implementing what the module
20 loader can already do, livepatch leverages existing code in the module
21 loader to perform the all the arch-specific relocation work. Specifically,
26 of arch-specific code required to port livepatch to a particular
34 selected from OS-specific ranges according to the definitions from glibc.
37 -----------------------------------------------------
39 reference non-exported global symbols and non-included local symbols.
40 Relocations referencing these types of symbols cannot be left in as-is
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/linux-6.14.4/samples/seccomp/
Dbpf-helper.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012 The Chromium OS Authors <chromium-os-[email protected]>
8 * The code may be used by anyone for any purpose,
17 #include "bpf-helper.h"
25 return -1; in bpf_resolve_jumps()
31 size_t offset = count - i - 1; in bpf_resolve_jumps() local
32 struct sock_filter *instr = &filter[offset]; in bpf_resolve_jumps()
33 if (instr->code != (BPF_JMP+BPF_JA)) in bpf_resolve_jumps()
35 switch ((instr->jt<<8)|instr->jf) { in bpf_resolve_jumps()
37 if (labels->labels[instr->k].location == 0xffffffff) { in bpf_resolve_jumps()
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/linux-6.14.4/include/linux/
Dpe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * - 0x1: initrd loading from the LINUX_EFI_INITRD_MEDIA_GUID device path,
17 * - 0x2: initrd loading using the initrd= command line option, where the file
30 * (https://lore.kernel.org/all/efd6f2d4-547c-1378-1faa-[email protected]/)
36 * LINUX_PE_MAGIC appears at offset 0x38 into the MS-DOS header of EFI bootable
129 #define IMAGE_SCN_TYPE_NO_PAD 0x00000008 /* don't pad - obsolete */
137 #define IMAGE_SCN_LNK_REMOVE 0x00000800 /* .o only - scn to be rm'd*/
138 #define IMAGE_SCN_LNK_COMDAT 0x00001000 /* .o only - COMDAT data */
147 /* and here they just stuck a 1-byte integer in the middle of a bitfield */
167 #define IMAGE_SCN_MEM_EXECUTE 0x20000000 /* can be executed as code */
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/linux-6.14.4/arch/arm/mach-omap2/
Domap_hwmod.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2011-2012 Texas Instruments, Inc.
15 * ------------
21 * TI's documentation, on-chip devices are referred to as "OMAP
26 * Most of the address and data flow between modules is via OCP-based
32 * OMAP hwmod provides a consistent way to describe the on-chip
37 * hwmod provides a way for other core code, such as the Linux device
38 * code or the OMAP power management and address space mapping code,
42 * -----------
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/linux-6.14.4/tools/testing/selftests/bpf/
Dtest_bpftool_synctypes.py2 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 import os, sys
10 LINUX_ROOT = os.path.abspath(os.path.join(__file__,
11 os.pardir, os.pardir, os.pardir, os.pardir, os.pardir))
12 BPFTOOL_DIR = os.getenv('BPFTOOL_DIR',
13 os.path.join(LINUX_ROOT, 'tools/bpf/bpftool'))
14 BPFTOOL_BASHCOMP_DIR = os.getenv('BPFTOOL_BASHCOMP_DIR',
15 os.path.join(BPFTOOL_DIR, 'bash-completion'))
16 BPFTOOL_DOC_DIR = os.getenv('BPFTOOL_DOC_DIR',
17 os.path.join(BPFTOOL_DIR, 'Documentation'))
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/linux-6.14.4/tools/perf/pmu-events/
Djevents.py2 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause)
3 """Convert directories of JSON events to C code."""
9 import os
63 def removesuffix(s: str, suffix: str) -> str:
69 return s[0:-len(suffix)] if s.endswith(suffix) else s
73 dirname: str) -> str:
79 return tblname.replace('-', '_')
82 def c_len(s: str) -> int:
87 \\. The code uses \000 rather than \0 as a terminator as an adjacent
90 \05). The code adjusts for \000 but not properly for all octal, hex
[all …]
/linux-6.14.4/lib/zlib_inflate/
Dinflate.h4 /* inflate.h -- internal inflate state definition
5 * Copyright (C) 1995-2004 Mark Adler
21 OS, /* i: waiting for extra flags and operating system (gzip) */ enumerator
29 TYPE, /* i: waiting for type bits, including last-flag bit */
34 LENLENS, /* i: waiting for code length code lengths */
35 CODELENS, /* i: waiting for length/lit and distance code lengths */
36 LEN, /* i: waiting for length/lit code */
38 DIST, /* i: waiting for distance code */
42 CHECK, /* i: waiting for 32-bit check value */
43 LENGTH, /* i: waiting for 32-bit length (gzip) */
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/registers/
Dgen_header.py3 # Copyright © 2019-2024 Google, Inc.
5 # SPDX-License-Identifier: MIT
9 import os
60 maxpos = parser.current_bitsize - 1
70 elif self.type == "float" and not (high - low == 31 or high - low == 15):
94 elif self.type == "float" and self.high - self.low == 31:
97 elif self.type == "float" and self.high - self.low == 15:
113 tab_count = (68 - (len(name) & ~7)) // 8
119 return ((0xffffffffffffffff >> (64 - (high + 1 - low))) << low)
126 # <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
[all …]
/linux-6.14.4/tools/perf/scripts/python/
Dintel-pt-events.py1 # SPDX-License-Identifier: GPL-2.0
2 # intel-pt-events.py: Print Intel PT Events including Power Events and PTWRITE
3 # Copyright (c) 2017-2021, Intel Corporation.
17 import os
26 sys.path.append(os.environ['PERF_EXEC_PATH'] + \
27 '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
47 glb_cpu = -1
77 ap.add_argument("--insn-trace", action='store_true')
78 ap.add_argument("--src-trace", action='store_true')
79 ap.add_argument("--all-switch-events", action='store_true')
[all …]
Darm-cs-trace-disasm.py1 # SPDX-License-Identifier: GPL-2.0
2 # arm-cs-trace-disasm.py: ARM CoreSight Trace Dump With Disassember
10 import os
11 from os import path
20 # Note a --kcore recording is required for accurate decode
29 # +-----------+-----------------+------------------+------------------+
31 # +-----------+-----------------+------------------+------------------+
32 # | --kcore | yes | no | yes |
34 # +-----------+-----------------+------------------+------------------+
38 # perf script -s scripts/python/arm-cs-trace-disasm.py -d
[all …]
/linux-6.14.4/arch/arm/mach-omap1/
Dtimer32k.c2 * linux/arch/arm/mach-omap1/timer32k.c
6 * Copyright (C) 2004 - 2005 Nokia Corporation
10 * OMAP Dual-mode timer framework support by Timo Teras
12 * MPU timer code based on the older MPU timer code for OMAP
58 * ---------------------------------------------------------------------------
59 * 32KHz OS timer
63 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
66 * ---------------------------------------------------------------------------
79 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
82 #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
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/linux-6.14.4/arch/arm/boot/dts/broadcom/
Dbcm47081-tplink-archer-c5-v2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
11 compatible = "tplink,archer-c5-v2", "brcm,bcm47081", "brcm,bcm4708";
12 model = "TP-LINK Archer C5 V2";
24 compatible = "gpio-leds";
26 led-2ghz {
31 led-lan {
36 led-usb2-port1 {
37 label = "bcm53xx:green:usb2-port1";
39 trigger-sources = <&ohci_port1>, <&ehci_port1>;
[all …]
Dbcm4709-tplink-archer-c9-v1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
11 compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708";
12 model = "TP-LINK Archer C9 V1";
24 compatible = "gpio-leds";
26 led-lan {
31 led-wps {
36 led-2ghz {
41 led-5ghz {
46 led-usb3 {
[all …]
/linux-6.14.4/Documentation/driver-api/gpio/
Ddriver.rst25 number, sometime also referred to as ``offset``, which is a unique number
26 between 0 and n-1, n being the number of GPIOs managed by the chip.
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
30 lines are handled by one bit per line in a 32-bit register, it makes sense to
44 So for example one platform could use global numbers 32-159 for GPIOs, with a
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
58 driver code:
60 - methods to establish GPIO line direction
[all …]
/linux-6.14.4/arch/arm/kernel/
Dentry-common.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-common.S
14 #include <asm/unistd-oabi.h>
19 #include "entry-header.S"
37 * have tracing, context tracking and rseq debug disabled - the overheads
45 ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
49 restore_user_regs fast = 1, offset = S_OFF
75 ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
81 /* Slower path - fall through to work_pending */
92 movlt scno, #(__NR_restart_syscall - __NR_SYSCALL_BASE)
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/cache/
Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <[email protected]>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
24 early secure boot code. Thus no need to deal with their configuration
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
[all …]
/linux-6.14.4/drivers/tee/amdtee/
Damdtee_if.h1 /* SPDX-License-Identifier: MIT */
8 * This file has definitions related to Host and AMD-TEE Trusted OS interface.
23 * struct memref - memory reference structure
25 * @offset: offset in bytes from beginning of the buffer
30 u32 offset; member
72 * non-contiguous. Below structures are meant to describe a shared memory region
77 * struct tee_sg_desc - sg descriptor for a physically contiguous buffer
89 * struct tee_sg_list - structure describing a scatter/gather list
102 * struct tee_cmd_map_shared_mem - command to map shared memory
112 * struct tee_cmd_unmap_shared_mem - command to unmap shared memory
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/gpio/
Dnvidia,tegra186-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
31 Code that wishes to configure access to the GPIO registers needs access
32 to these registers to do so. Code which simply wishes to read or write
52 port, and the mapping from port name to register offset within a
53 controller, are both extremely non-linear. The header file
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/linux-6.14.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_virt.h29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
42 /* error code for indirect register access path supported by rlcg for sriov */
50 /* all asic after AI use this offset */
52 /* tonga/fiji use this offset */
71 /* struct error_entry - amdgpu VF error information. */
76 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; member
84 * struct amdgpu_virt_ops - amdgpu device virt operations
120 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
180 /* guest OS type and version: need a define */
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