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/linux-6.14.4/Documentation/devicetree/bindings/leds/
Dleds-bcm6328.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-bcm6328.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <[email protected]>
17 as spi-gpio. See
21 exporting the 74x164 as spi-gpio prevents those LEDs to be hardware
25 should be controlled by a hardware signal instead of the MODE register value,
27 is usually 1:1 for hardware to LED signals, but through the activity/link
29 explained later in brcm,link-signal-sources). Even if a LED is hardware
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/linux-6.14.4/arch/mips/boot/dts/brcm/
Dbcm63268-comtrend-vr-3032u.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 compatible = "comtrend,vr-3032u", "brcm,bcm63268";
8 model = "Comtrend VR-3032u";
17 stdout-path = &uart0;
23 brcm,serial-leds;
24 brcm,serial-dat-low;
25 brcm,serial-shift-inv;
29 brcm,hardware-controlled;
30 brcm,link-signal-sources = <0>;
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/linux-6.14.4/drivers/leds/
Dleds-bcm6328.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for BCM6328 memory-mapped LEDs, based on leds-syscon.c
59 * struct bcm6328_led - state container for bcm6328 based LEDs
98 * bits [31:0] -> LEDs 8-23
99 * bits [47:32] -> LEDs 0-7
100 * bits [63:48] -> unused
105 return pin + 16; /* LEDs 0-7 (bits 47:32) */ in bcm6328_pin2shift()
107 return pin - 8; /* LEDs 8-23 (bits 31:0) */ in bcm6328_pin2shift()
115 shift = bcm6328_pin2shift(led->pin); in bcm6328_led_mode()
117 mode = led->mem + BCM6328_REG_MODE_HI; in bcm6328_led_mode()
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/linux-6.14.4/Documentation/userspace-api/media/mediactl/
Dmedia-types.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _media-controller-types:
10 .. _media-entity-functions:
11 .. _MEDIA-ENT-F-UNKNOWN:
12 .. _MEDIA-ENT-F-V4L2-SUBDEV-UNKNOWN:
13 .. _MEDIA-ENT-F-IO-V4L:
14 .. _MEDIA-ENT-F-IO-VBI:
15 .. _MEDIA-ENT-F-IO-SWRADIO:
16 .. _MEDIA-ENT-F-IO-DTV:
17 .. _MEDIA-ENT-F-DTV-DEMOD:
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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
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/linux-6.14.4/drivers/comedi/drivers/
Dni_routes.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
33 * struct ni_route_set - Set of destinations with a common source.
34 * @dest: Destination of all sources in this route set.
35 * @n_src: Number of sources for this route set.
36 * @src: List of sources that all map to the same destination.
45 * struct ni_device_routes - List of all src->dest sets for a particular device.
46 * @device: Name of board/device (e.g. pxi-6733).
57 * struct ni_route_tables - Register values and valid routes for a device.
62 * Link to the valid src->dest routes and the register values used to assign
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/linux-6.14.4/Documentation/driver-api/
Dpps.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PPS - Pulse Per Second
22 --------
25 system several PPS sources.
28 provides a high precision signal each second so that an application
32 Carrier Detect pin) or to a parallel port (ACK-pin) or to a special
38 GPS receiver as PPS source, to obtain a wallclock-time with
39 sub-millisecond synchronisation to UTC.
43 ------------------
46 CPU GPIO-Pin as physical link to the signal, I encountered a deeper
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/linux-6.14.4/Documentation/sound/soc/
Dclocking.rst10 ------------
13 or SYSCLK). This audio master clock can be derived from a number of sources
23 ----------
25 as BCLK). This clock is used to drive the digital audio data across the link
28 The DAI also has a frame clock to signal the start of each audio frame. This
32 Bit Clock can be generated as follows:-
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
46 ------------------------
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Ddapm.rst11 management frameworks and, as such, can easily co-exist with them.
32 The graph for the STM32MP1-DK1 sound card is shown in picture:
34 .. kernel-figure:: dapm-graph.svg
39 `tools/sound/dapm-graph` utility.
60 audio subsystem signal paths
78 Mixes several analog signals into a single analog signal.
112 Signal Generator.
117 DAI Link
118 DAI Link between two DAI structures
142 (Widgets are defined in include/sound/soc-dapm.h)
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/linux-6.14.4/Documentation/sound/hd-audio/
Drealtek-pc-beep.rst20 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
24 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
43 into 21h (headphone jack on my machine). Mixed signal respects the mute
48 into 14h (internal speaker on my machine). Mixed signal **ignores** the mute
58 +--DIV--+--!DIV--+ {1Ah boost control}
60 +--(b == 0)--+--(b != 0)--+
70 +-----!h-----+-----S-----+
79 All Realtek HDA codecs have a vendor-defined widget with node ID 20h which
92 Specifically, it selects between two sources for the input pin widget with Node
93 ID (NID) 1Ah: the widget's signal can come either from an audio jack (on my
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/linux-6.14.4/drivers/net/phy/
Ddp83822.c1 // SPDX-License-Identifier: GPL-2.0
139 #define DP83822_LED_FN_LINK 0x0 /* Link established */
144 #define DP83822_LED_FN_LINK_100_BTX 0x5 /* 100 BTX link established */
145 #define DP83822_LED_FN_LINK_10_BT 0x6 /* 10BT link established */
147 #define DP83822_LED_FN_LINK_RX_TX 0x8 /* Link established, blink for rx or tx activity */
148 #define DP83822_LED_FN_ACTIVE_STRETCH 0x9 /* Active Stretch Signal */
149 #define DP83822_LED_FN_MII_LINK 0xa /* MII LINK (100BT+FD) */
152 #define DP83822_LED_FN_LINK_LOST 0xd /* Link Lost */
205 struct net_device *ndev = phydev->attached_dev; in dp83822_config_wol()
209 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { in dp83822_config_wol()
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/linux-6.14.4/drivers/media/i2c/
Dmax9286.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017-2019 Jacopo Mondi
6 * Copyright (C) 2017-2019 Kieran Bingham
7 * Copyright (C) 2017-2019 Laurent Pinchart
8 * Copyright (C) 2017-2019 Niklas Söderlund
20 #include <linux/i2c-mux.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
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/linux-6.14.4/drivers/input/touchscreen/
Dwm9705.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm9705.c -- Codec driver for Wolfson WM9705 AC97 Codec.
56 * touchpanel plate and the ADC sampling the signal.
84 * Sources of glitch noise, such as signals driving an LCD display, may feed
86 * order to minimise this, a signal may be applied to the MASK pin to delay or
102 21, /* 1 AC97 Link frames */
123 * The delay is 3 AC97 link frames + the touchpanel settling delay
147 dev_dbg(wm->dev, in wm9705_phy_init()
150 dev_dbg(wm->dev, in wm9705_phy_init()
158 dev_dbg(wm->dev, "supplied delay out of range."); in wm9705_phy_init()
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Dwm9713.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm9713.c -- Codec touch driver for Wolfson WM9713 AC97 Codec.
69 * touchpanel plate and the ADC sampling the signal.
87 MODULE_PARM_DESC(five_wire, "Set to '1' to use 5-wire touchscreen.");
92 * Sources of glitch noise, such as signals driving an LCD display, may feed
94 * order to minimise this, a signal may be applied to the MASK pin to delay or
120 21, /* 1 AC97 Link frames */
141 * The delay is 3 AC97 link frames + the touchpanel settling delay
163 dev_info(wm->dev, "setting pen detect pull-up to %d Ohms\n", in wm9713_phy_init()
170 dev_info(wm->dev, "setting 5-wire touchscreen mode."); in wm9713_phy_init()
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Dwm9712.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm9712.c -- Codec driver for Wolfson WM9712 AC97 Codecs.
69 * touchpanel plate and the ADC sampling the signal.
87 MODULE_PARM_DESC(five_wire, "Set to '1' to use 5-wire touchscreen.");
92 * Sources of glitch noise, such as signals driving an LCD display, may feed
94 * order to minimise this, a signal may be applied to the MASK pin to delay or
120 21, /* 1 AC97 Link frames */
141 * The delay is 3 AC97 link frames + the touchpanel settling delay
160 dev_dbg(wm->dev, "setting pen detect pull-up to %d Ohms\n", in wm9712_phy_init()
167 dev_dbg(wm->dev, "setting 5-wire touchscreen mode.\n"); in wm9712_phy_init()
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/linux-6.14.4/include/media/
Dmedia-entity.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * enum media_gobj_type - type of a graph object
30 * @MEDIA_GRAPH_LINK: Identify a media link
42 #define MEDIA_BITS_PER_ID (32 - MEDIA_BITS_PER_TYPE)
43 #define MEDIA_ID_MASK GENMASK_ULL(MEDIA_BITS_PER_ID - 1, 0)
48 * struct media_gobj - Define a graph object.
51 * @id: Non-zero object ID identifier. The ID should be unique
55 * @list: List entry stored in one of the per-type mdev object lists
68 * struct media_entity_enum - An enumeration of media entities.
71 * media_entity->internal_idx.
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/hwss/dce110/
Ddce110_hwseq.c50 #include "link.h"
74 * For eDP, after power-up/power/down,
84 hws->ctx
87 ctx->logger
89 struct dc_context *ctx = dc->ctx
92 hws->regs->reg
96 hws->shifts->field_name, hws->masks->field_name
104 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
107 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
110 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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/linux-6.14.4/drivers/hwtracing/intel_th/
Dgth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Intel Corporation.
25 * struct gth_output - GTH view on an output port
27 * @output: link to output device's output descriptor
41 * struct gth_device - GTH device
68 val = ioread32(gth->base + reg); in gth_output_set()
71 iowrite32(val, gth->base + reg); in gth_output_set()
80 val = ioread32(gth->base + reg); in gth_output_get()
94 val = ioread32(gth->base + reg); in gth_smcfreq_set()
97 iowrite32(val, gth->base + reg); in gth_smcfreq_set()
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/linux-6.14.4/drivers/pci/controller/
Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/pci-ecam.h>
29 #include "../pci-bridge-emul.h"
139 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
294 writel(val, pcie->base + reg); in advk_writel()
299 return readl(pcie->base + reg); in advk_readl()
314 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
322 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
324 * is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0, in advk_pcie_link_active()
325 * L0s, L1 and L2 states. And according to 3.2.1. Data Link in advk_pcie_link_active()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 #include "link.h"
49 #include "link/hwss/link_hwss_dio.h"
50 #include "link/hwss/link_hwss_dpia.h"
51 #include "link/hwss/link_hwss_hpo_dp.h"
52 #include "link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h"
53 #include "link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h"
95 dc->ctx->logger
100 #define UNABLE_TO_SPLIT -1
230 init_data->num_virtual_links, dc); in dc_create_resource_pool()
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/linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/
Ddcsr.txt21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,dcsr", "simple-bus";
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c43 #include "link/protocols/link_dpcd.h"
45 #include "link/protocols/link_dp_capability.h"
46 #include "link/protocols/link_ddc.h"
101 #include <media/cec-notifier.h>
183 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) in get_subconnector_type() argument
185 switch (link->dpcd_caps.dongle_type) { in get_subconnector_type()
204 struct dc_link *link = aconnector->dc_link; in update_subconnector_property() local
205 struct drm_connector *connector = &aconnector->base; in update_subconnector_property()
208 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) in update_subconnector_property()
211 if (aconnector->dc_sink) in update_subconnector_property()
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/linux-6.14.4/drivers/gpu/ipu-v3/
Dipu-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
26 #include <video/imx-ipu-v3.h>
27 #include "ipu-prv.h"
31 return readl(ipu->cm_reg + offset); in ipu_cm_read()
36 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
41 return ipu->id; in ipu_get_num()
157 return -EINVAL; in ipu_degrees_to_rot_mode()
193 return -EINVAL; in ipu_rot_mode_to_degrees()
204 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
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/linux-6.14.4/include/sound/
Demu10k1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
41 // This is used to define hardware bit-fields (sub-registers) by combining
44 // The non-concatenating (_NC) variant should be used directly only for
45 // sub-registers that do not follow the <register>_<field> naming pattern.
55 // Macros for manipulating values of bit-fields declared using the above macros.
59 // single sub-register at a time.
62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn401/
Ddcn401_resource.c1 // SPDX-License-Identifier: MIT
53 #include "link.h"
98 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
126 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
129 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
175 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
189 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
700 .dwb_fi_phase = -1, // -1 = disable,
765 ctx->dc->caps.extended_aux_timeout_support); in dcn401_aux_engine_create()
767 return &aux_engine->base; in dcn401_aux_engine_create()
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