Home
last modified time | relevance | path

Searched +full:ipq9574 +full:- +full:cmn +full:- +full:pll (Results 1 – 7 of 7) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dqcom,ipq9574-cmn-pll.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm CMN PLL Clock Controller on IPQ SoC
10 - Bjorn Andersson <[email protected]>
11 - Luo Jie <[email protected]>
14 The CMN (or common) PLL clock controller expects a reference
15 input clock. This reference clock is from the on-board Wi-Fi.
16 The CMN PLL supplies a number of fixed rate output clocks to
[all …]
/linux-6.14.4/drivers/clk/qcom/
Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
19 * +---------+
21 * +--+---+--+
24 * +-------+---+------+
25 * | +-------------> eth0-50mhz
26 * REF CLK | IPQ9574 |
27 * -------->+ +-------------> eth1-50mhz
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
86 tristate "MSM8916 A53 PLL"
88 Support for the A53 PLL on MSM8916 devices. It provides
94 tristate "A7 PLL driver for SDX55 and SDX65"
96 Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
183 tristate "IPQ APSS PLL"
185 Support for APSS PLL on ipq devices. The APSS PLL is the main
203 tristate "IPQ CMN PLL Clock Controller"
205 Support for CMN PLL clock controller on IPQ platform. The
206 CMN PLL consumes the AHB/SYS clocks from GCC and supplies
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
[all …]
/linux-6.14.4/include/dt-bindings/clock/
Dqcom,ipq-cmn-pll.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
9 /* CMN PLL core clock. */
12 /* The output clocks from CMN PLL of IPQ9574. */
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dipq9574-rdp-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * IPQ9574 RDP board common device tree source
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
14 #include "ipq9574.dtsi"
22 stdout-path = "serial0:115200n8";
[all …]
Dipq9574.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * IPQ9574 SoC device tree source
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
11 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
12 #include <dt-bindings/interconnect/qcom,ipq9574.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
[all …]