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/linux-6.14.4/drivers/net/ethernet/freescale/enetc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 drivers for the NXP ENETC controller.
8 If compiled as module (M), the module name is fsl-enetc-core.
14 different versions of NXP ENETC PF controllers.
16 If compiled as module (M), the module name is nxp-enetc-pf-common.
19 tristate "ENETC PF driver"
30 This driver supports NXP ENETC gigabit ethernet controller PCIe
31 physical function (PF) devices, managing ENETC Ports at a privileged
34 If compiled as module (M), the module name is fsl-enetc.
46 This driver supports NXP ENETC devices with major revision 4. ENETC is
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_FSL_ENETC_CORE) += fsl-enetc-core.o
4 fsl-enetc-core-y := enetc.o enetc_cbdr.o enetc_ethtool.o
6 obj-$(CONFIG_NXP_ENETC_PF_COMMON) += nxp-enetc-pf-common.o
7 nxp-enetc-pf-common-y := enetc_pf_common.o
9 obj-$(CONFIG_FSL_ENETC) += fsl-enetc.o
10 fsl-enetc-y := enetc_pf.o
11 fsl-enetc-$(CONFIG_PCI_IOV) += enetc_msg.o
12 fsl-enetc-$(CONFIG_FSL_ENETC_QOS) += enetc_qos.o
14 obj-$(CONFIG_NXP_ENETC4) += nxp-enetc4.o
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Denetc_pf_common.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
13 struct enetc_hw *hw = &pf->si->hw; in enetc_set_si_hw_addr()
15 pf->ops->set_si_primary_mac(hw, si, mac_addr); in enetc_set_si_hw_addr()
20 struct enetc_hw *hw = &pf->si->hw; in enetc_get_si_hw_addr()
22 pf->ops->get_si_primary_mac(hw, si, mac_addr); in enetc_get_si_hw_addr()
28 struct enetc_pf *pf = enetc_si_priv(priv->si); in enetc_pf_set_mac_addr()
31 if (!is_valid_ether_addr(saddr->sa_data)) in enetc_pf_set_mac_addr()
32 return -EADDRNOTAVAIL; in enetc_pf_set_mac_addr()
34 eth_hw_addr_set(ndev, saddr->sa_data); in enetc_pf_set_mac_addr()
35 enetc_set_si_hw_addr(pf, 0, saddr->sa_data); in enetc_pf_set_mac_addr()
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Denetc_hw.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
11 /* ENETC device IDs */
16 /* ENETC register block BAR */
32 /* cache attribute registers for transactions initiated by ENETC */
47 /* VF-PF Message passing */
110 /** SI BDR sub-blocks, n = 0..7 */
393 /* ENETC register accessors */
395 /* MDIO issue workaround (on LS1028A) -
396 * Due to a hardware issue, an access to MDIO registers
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Denetc_pf.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
4 #include "enetc.h"
65 struct mii_bus *mdio; /* saved for cleanup */ member
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dfsl,enetc-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,enetc-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ENETC external MDIO PCIe endpoint device
10 NETC provides an external master MDIO interface (EMDIO) for managing external
12 provides a means for different software modules to share a single set of MDIO
16 - Frank Li <[email protected]>
17 - Vladimir Oltean <[email protected]>
18 - Wei Fang <[email protected]>
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Dfsl,enetc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,enetc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The NIC functionality in NETC is known as EtherNET Controller (ENETC). ENETC
12 (SR-IOV), advanced QoS with 8 traffic classes and 4 drop resilience levels,
16 - Frank Li <[email protected]>
17 - Vladimir Oltean <[email protected]>
18 - Wei Fang <[email protected]>
19 - Claudiu Manoil <[email protected]>
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Dnxp,netc-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,netc-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 block (IERB) and privileged register block (PRB). IERB is used for pre-boot
12 initialization for all NETC devices, such as ENETC, Timer, EMIDO and so on.
18 - Wei Fang <[email protected]>
19 - Clark Wang <[email protected]>
24 - nxp,imx95-netc-blk-ctrl
29 reg-names:
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/linux-6.14.4/drivers/net/ethernet/freescale/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 Say Y here if you want to use the built-in 10/100 Fast ethernet
45 This option enables support for the MPC5200's on-chip
50 bool "FEC MPC52xx MDIO bus driver"
55 an external MII PHY chip or 10 Mbps 7-wire interface
65 tristate "Freescale PQ MDIO"
68 This driver supports the MDIO bus used by the gianfar and UCC drivers.
71 tristate "Freescale XGMAC MDIO"
77 This driver supports the MDIO bus on the Fman 10G Ethernet MACs, and
107 source "drivers/net/ethernet/freescale/enetc/Kconfig"
/linux-6.14.4/Documentation/devicetree/bindings/net/dsa/
Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <[email protected]>
11 - Claudiu Manoil <[email protected]>
12 - Alexandre Belloni <[email protected]>
13 - [email protected]
16 There are multiple switches which are either part of the Ocelot-1 family, or
22 Frame DMA or register-based I/O.
26 This is found in the NXP T1040, where it is a memory-mapped platform
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/linux-6.14.4/drivers/net/pcs/
Dpcs-lynx.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Lynx PCS MDIO helpers
6 #include <linux/mdio.h>
8 #include <linux/pcs-lynx.h>
25 struct mdio_device *mdio; member
36 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
62 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
63 int addr = pcs->addr; in lynx_pcs_get_state_usxgmii()
70 state->link = !!(status & MDIO_STAT1_LSTATUS); in lynx_pcs_get_state_usxgmii()
71 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE); in lynx_pcs_get_state_usxgmii()
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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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/linux-6.14.4/drivers/net/dsa/ocelot/
Dfelix_vsc9959.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2018-2019 NXP
15 #include <linux/pcs-lynx.h>
18 #include <linux/mdio.h>
554 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
663 /* Layer-3 Information */
669 /* Layer-4 Information */
900 /* soft-reset the switch core */ in vsc9959_reset()
906 dev_err(ocelot->dev, "timeout: switch core reset\n"); in vsc9959_reset()
916 dev_err(ocelot->dev, "timeout: switch sram init\n"); in vsc9959_reset()
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/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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