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/linux-6.14.4/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
48 #define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */
49 #define MDIO_PCS_EEE_ABLE2 21 /* EEE Capability register 2 */
51 #define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */
53 #define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
54 #define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */
55 #define MDIO_AN_EEE_ADV2 62 /* EEE advertisement 2 */
56 #define MDIO_AN_EEE_LPABLE2 63 /* EEE link partner ability 2 */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
[all …]
/linux-6.14.4/drivers/net/pcs/
Dpcs-xpcs.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/pcs/pcs-xpcs.h>
60 /* EEE Mode Control Register */
93 /* VR MII EEE Control 0 defines */
103 /* VR MII EEE Control 1 defines */
107 static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma }
122 struct phylink_pcs pcs; member
/linux-6.14.4/include/linux/
Dphylink.h8 #include <net/eee.h>
24 MLO_AN_FIXED, /* Fixed-link mode */
25 MLO_AN_INBAND, /* In-band protocol */
27 /* PCS "negotiation" mode.
28 * PHYLINK_PCS_NEG_NONE - protocol has no inband capability
29 * PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
30 * PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
31 * 1000base-X with autoneg off
32 * PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
34 * PHYLINK_PCS_NEG_INBAND - inband mode selected
[all …]
/linux-6.14.4/drivers/net/phy/
Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
4 * technologies such as SFP cages where the PHY is hot-pluggable.
44 * struct phylink - internal data type for phylink
51 struct phylink_pcs *pcs; member
61 u8 link_port; /* The current non-phy ethtool port */
103 if ((pl)->config->type == PHYLINK_NETDEV) \
104 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
105 else if ((pl)->config->type == PHYLINK_DEV) \
106 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
118 if ((pl)->config->type == PHYLINK_NETDEV) \
[all …]
/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
18 #include <linux/pcs/pcs-xpcs.h>
58 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
159 /* EEE */
191 /* PCS */
274 /* PCS defines */
278 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
283 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
287 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
[all …]
Dstmmac_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
98 /* EEE */
130 /* PCS */
306 if (priv->plat->has_gmac || priv->plat->has_gmac4) in stmmac_ethtool_getdrvinfo()
307 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); in stmmac_ethtool_getdrvinfo()
308 else if (priv->plat->has_xgmac) in stmmac_ethtool_getdrvinfo()
309 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); in stmmac_ethtool_getdrvinfo()
311 strscpy(info->driver, MAC100_ETHTOOL_NAME, in stmmac_ethtool_getdrvinfo()
312 sizeof(info->driver)); in stmmac_ethtool_getdrvinfo()
[all …]
Ddwmac1000_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
45 switch (axi->axi_blen[i]) { in dwmac1000_dma_axi()
77 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; in dwmac1000_dma_init_channel()
78 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; in dwmac1000_dma_init_channel()
[all …]
Dstmmac_main.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
29 #include <linux/dma-mapping.h>
56 * with fine resolution and binary rollover. This avoid non-monotonic behavior
63 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
71 static int debug = -1;
73 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
75 static int phyaddr = -1;
79 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4)
[all …]
Ddwmac4_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
26 if (axi->axi_lpi_en) in dwmac4_dma_axi()
28 if (axi->axi_xit_frm) in dwmac4_dma_axi()
32 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
36 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
44 switch (axi->axi_blen[i]) { in dwmac4_dma_axi()
77 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; in dwmac4_dma_init_rx_chan()
79 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; in dwmac4_dma_init_rx_chan()
85 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) in dwmac4_dma_init_rx_chan()
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Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
59 /* Energy Efficient Ethernet (EEE)
79 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
81 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
85 #define GMAC_PCS_BASE 0x000000c0 /* PCS register base */
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
177 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
196 /*--- DMA BLOCK defines ---*/
[all …]
/linux-6.14.4/drivers/net/ethernet/intel/igb/
De1000_82575.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
[all …]
De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
271 /* 1000/H is not supported, nor spec-compliant. */
309 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
[all …]
De1000_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
[all …]
/linux-6.14.4/drivers/net/ethernet/freescale/fman/
Dfman_memac.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
14 #include <linux/pcs-lynx.h>
56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
64 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
[all …]
/linux-6.14.4/drivers/net/dsa/b53/
Db53_priv.h4 * Copyright (C) 2011-2013 Jonas Gorski <[email protected]>
87 struct phylink_pcs pcs; member
98 struct ethtool_keee eee; member
152 struct b53_pcs pcs[B53_N_PCS]; member
157 if (dev->enabled_ports & BIT(i))
162 return dev->chip_id == BCM5325_DEVICE_ID; in is5325()
168 return dev->chip_id == BCM5365_DEVICE_ID; in is5365()
176 return dev->chip_id == BCM5397_DEVICE_ID || in is5397_98()
177 dev->chip_id == BCM5398_DEVICE_ID; in is5397_98()
182 return dev->chip_id == BCM5395_DEVICE_ID || in is539x()
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/linux-6.14.4/drivers/platform/x86/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 x86 platforms, including vendor-specific laptop extension drivers.
23 This driver adds support for the ACPI-WMI (Windows Management
26 ACPI-WMI is a proprietary extension to ACPI to expose parts of the
27 ACPI firmware to userspace - this is done through various vendor
38 any ACPI-WMI devices.
45 Say Y here if you want to be able to read a firmware-embedded
50 be called wmi-bmof.
63 control, fn-lock, mic-mute LED, and other extra features.
66 will be called huawei-wmi.
[all …]
/linux-6.14.4/drivers/net/dsa/qca/
Dqca8k.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2011-2012 Gabor Juhos <[email protected]>
92 #define QCA8K_LED_COUNT ((QCA8K_NUM_PORTS - QCA8K_NUM_CPU_PORTS) * QCA8K_LED_PORT_COUNT)
97 #define QCA8K_LED_PHY123_PATTERN_EN_SHIFT(_phy, _led) ((((_phy) - 1) * 6) + 8 + (2 * (_led)))
174 /* EEE control registers */
280 /* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */
426 struct phylink_pcs pcs; member
497 return port - 1; in qca8k_port_to_phy()
521 /* Common eee function */
522 int qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *eee);
/linux-6.14.4/drivers/net/ethernet/intel/e1000e/
Dich8lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
[all …]
Dethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
28 "s0ix-enabled",
36 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
41 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
115 struct e1000_hw *hw = &adapter->hw; in e1000_get_link_ksettings()
117 if (hw->phy.media_type == e1000_media_type_copper) { in e1000_get_link_ksettings()
127 if (hw->phy.type == e1000_phy_ife) in e1000_get_link_ksettings()
131 if (hw->mac.autoneg == 1) { in e1000_get_link_ksettings()
134 advertising |= hw->phy.autoneg_advertised; in e1000_get_link_ksettings()
[all …]
/linux-6.14.4/Documentation/networking/
Dphy.rst26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
208 Now just make sure that phydev->supported and phydev->advertising have any
[all …]
/linux-6.14.4/drivers/net/dsa/
Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
28 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) in pcs_to_mt753x_pcs() argument
30 return container_of(pcs, struct mt753x_pcs, pcs); in pcs_to_mt753x_pcs()
81 if (priv->bus) in mt7530_mutex_lock()
82 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
88 if (priv->bus) in mt7530_mutex_unlock()
89 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
95 struct mii_bus *bus = priv->bus; in core_write()
101 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
107 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/linux-6.14.4/drivers/net/ethernet/marvell/
Dmvneta.c7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
270 * to cover all rate-limit values from 10Kbps up to 5Gbps
300 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
378 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
381 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
490 /* Pointer to the CPU-local NAPI struct */
599 u32 reserved2; /* hw_cmd - (for future use, PMT) */
600 u32 reserved3[4]; /* Reserved - (for future use) */
[all …]
/linux-6.14.4/drivers/net/ethernet/marvell/mvpp2/
Dmvpp2_main.c1 // SPDX-License-Identifier: GPL-2.0
76 writel(data, priv->swth_base[0] + offset); in mvpp2_write()
81 return readl(priv->swth_base[0] + offset); in mvpp2_read()
86 return readl_relaxed(priv->swth_base[0] + offset); in mvpp2_read_relaxed()
91 return cpu % priv->nthreads; in mvpp2_cpu_to_thread()
96 writel(data, priv->cm3_base + offset); in mvpp2_cm3_write()
101 return readl(priv->cm3_base + offset); in mvpp2_cm3_read()
124 * - per-thread registers, where each thread has its own copy of the
140 * - global registers that must be accessed through a specific thread
141 * window, because they are related to an access to a per-thread
[all …]

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