/linux-6.14.4/arch/arm/boot/dts/ti/omap/ |
D | omap24xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "ti,composite-mux-clock"; 12 ti,bit-shift = <2>; 17 #clock-cells = <0>; 18 compatible = "ti,composite-clock"; 23 #clock-cells = <0>; 24 compatible = "ti,composite-mux-clock"; 26 ti,bit-shift = <6>; 31 #clock-cells = <0>; [all …]
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D | omap2430-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #clock-cells = <0>; 11 compatible = "ti,composite-mux-clock"; 17 #clock-cells = <0>; 18 compatible = "ti,composite-clock"; 23 #clock-cells = <0>; 24 compatible = "ti,composite-mux-clock"; 26 ti,bit-shift = <2>; 31 #clock-cells = <0>; 32 compatible = "ti,composite-clock"; [all …]
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D | omap2420-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #clock-cells = <0>; 11 compatible = "ti,composite-no-wait-gate-clock"; 13 ti,bit-shift = <15>; 18 #clock-cells = <0>; 19 compatible = "ti,composite-mux-clock"; 21 ti,bit-shift = <8>; 26 #clock-cells = <0>; 27 compatible = "ti,composite-clock"; 32 #clock-cells = <0>; [all …]
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D | omap44xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "extalt_clkin_ck"; 12 clock-frequency = <59000000>; 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 clock-output-names = "pad_clks_src_ck"; 19 clock-frequency = <12000000>; 23 #clock-cells = <0>; [all …]
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D | omap54xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "pad_clks_src_ck"; 12 clock-frequency = <12000000>; 16 #clock-cells = <0>; 17 compatible = "ti,gate-clock"; 18 clock-output-names = "pad_clks_ck"; 20 ti,bit-shift = <8>; 25 #clock-cells = <0>; [all …]
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/linux-6.14.4/include/linux/ |
D | bitops.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 25 * Defined here because those may be needed by architecture-specific static 29 #include <asm-generic/bitops/generic-non-atomic.h> 32 * Many architecture-specific non-atomic bitops contain inline asm code and due 33 * to that the compiler can't optimize them to compile-time expressions or 37 * equal to `unsigned long foo = BIT(BAR)`, pick the generic C alternative when 40 * The casts to `uintptr_t` are needed to mitigate `-Waddress` warnings when 41 * passing a bitmap from .bss or .data (-> `!!addr` is always true). 51 * The following macros are non-atomic versions of their non-underscored 92 return order; /* We could be slightly more clever with -1 here... */ in get_bitmask_order() [all …]
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D | math64.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder 17 * @dividend: unsigned 64bit dividend 18 * @divisor: unsigned 32bit divisor 19 * @remainder: pointer to unsigned 32bit remainder 23 * This is commonly provided by 32bit archs to provide an optimized 64bit 33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder 34 * @dividend: signed 64bit dividend 35 * @divisor: signed 32bit divisor 36 * @remainder: pointer to signed 32bit remainder [all …]
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D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]> 4 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]> 14 * top-level framework. custom flags for dealing with hardware specifics 19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ [all …]
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/linux-6.14.4/drivers/memory/tegra/ |
D | tegra114.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <dt-bindings/memory/tegra114-mc.h> 21 .shift = 0, 33 .bit = 1, 37 .shift = 0, 49 .bit = 2, 53 .shift = 0, 65 .bit = 3, 69 .shift = 16, 81 .bit = 4, [all …]
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D | tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 #include <dt-bindings/memory/tegra210-mc.h> 22 .bit = 1, 26 .shift = 0, 38 .bit = 2, 42 .shift = 0, 54 .bit = 3, 58 .shift = 16, 70 .bit = 4, 74 .shift = 16, [all …]
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D | tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #include <dt-bindings/memory/tegra124-mc.h> 22 .shift = 0, 34 .bit = 1, 38 .shift = 0, 50 .bit = 2, 54 .shift = 0, 66 .bit = 3, 70 .shift = 16, 82 .bit = 4, [all …]
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D | tegra30.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #include <dt-bindings/memory/tegra30-mc.h> 43 .shift = 0, 56 .bit = 1, 60 .shift = 0, 73 .bit = 2, 77 .shift = 0, 90 .bit = 3, 94 .shift = 16, 107 .bit = 4, [all …]
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/linux-6.14.4/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
D | phy_qmath.c | 1 // SPDX-License-Identifier: ISC 9 * Description: This function make 16 bit unsigned multiplication. 10 * To fit the output into 16 bits the 32 bit multiplication result is right 19 * Description: This function make 16 bit multiplication and return the result 22 * is done to remove the extra sign bit formed due to the multiplication. 23 * When both the 16bit inputs are 0x8000 then the output is saturated to 38 * Description: This function add two 32 bit numbers and return the 32bit 55 * Description: This function add two 16 bit numbers and return the 16bit 74 * Description: This function make 16 bit subtraction and return the 16bit 81 s32 temp = (s32) op1 - (s32) op2; in qm_sub16() [all …]
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/linux-6.14.4/drivers/gpio/ |
D | gpio-tangier.c | 1 // SPDX-License-Identifier: GPL-2.0-only 22 #include <linux/pinctrl/pinconf-generic.h> 30 #include "gpio-tangier.h" 46 * struct tng_gpio_context - Context to be saved during suspend-resume 69 return priv->reg_base + reg + reg_offset * 4; in gpio_reg() 73 unsigned int reg, u8 *bit) in gpio_reg_and_bit() argument 77 u8 shift = offset % 32; in gpio_reg_and_bit() local 79 *bit = shift; in gpio_reg_and_bit() 80 return priv->reg_base + reg + reg_offset * 4; in gpio_reg_and_bit() 86 u8 shift; in tng_gpio_get() local [all …]
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/linux-6.14.4/lib/math/ |
D | div64.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Based on former do_div() implementation from asm-parisc/div64.h: 6 * Copyright (C) 1999 Hewlett-Packard Co 7 * Copyright (C) 1999 David Mosberger-Tang <[email protected]> 10 * Generic C version of 64bit/32bit division and modulo, with 11 * 64bit result and 32bit remainder. 16 * for some CPUs. __div64_32() can be overridden by linking arch-specific 28 /* Not needed on 64bit architectures */ 39 /* Reduce the thing a bit first */ in __div64_32() 44 rem -= (uint64_t) (high*base) << 32; in __div64_32() [all …]
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/linux-6.14.4/arch/arm64/lib/ |
D | insn.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * Copyright (C) 2014-2016 Zi Shen Lim <[email protected]> 14 #include <asm/debug-monitors.h> 19 #define AARCH64_INSN_SF_BIT BIT(31) 20 #define AARCH64_INSN_N_BIT BIT(22) 21 #define AARCH64_INSN_LSL_12 BIT(22) 27 int shift; in aarch64_get_imm_shift_mask() local 31 mask = BIT(26) - 1; in aarch64_get_imm_shift_mask() 32 shift = 0; in aarch64_get_imm_shift_mask() 35 mask = BIT(19) - 1; in aarch64_get_imm_shift_mask() [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/regulator/ |
D | anatop-regulator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ying-Chun Liu (PaulLiu) <[email protected]> 13 - $ref: regulator.yaml# 17 const: fsl,anatop-regulator 19 regulator-name: true 21 anatop-reg-offset: 25 anatop-vol-bit-shift: [all …]
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/linux-6.14.4/drivers/net/ethernet/intel/igc/ |
D | igc_leds.c | 1 // SPDX-License-Identifier: GPL-2.0 16 #define IGC_LEDCTL_LED0_BLINK BIT(7) 19 #define IGC_LEDCTL_LED1_BLINK BIT(15) 22 #define IGC_LEDCTL_LED2_BLINK BIT(23) 33 (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK_1000) | \ 34 BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_10) | \ 35 BIT(TRIGGER_NETDEV_RX) | BIT(TRIGGER_NETDEV_TX)) 38 (BIT(TRIGGER_NETDEV_RX) | BIT(TRIGGER_NETDEV_TX)) 50 u32 *mask, u32 *shift, u32 *blink) in igc_led_select() argument 55 *shift = IGC_LEDCTL_LED0_MODE_SHIFT; in igc_led_select() [all …]
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/linux-6.14.4/drivers/clk/sprd/ |
D | sc9860-clk.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/clk-provider.h> 16 #include <dt-bindings/clock/sprd,sc9860-clk.h> 25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m", 27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m", 29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m", 31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m", 33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m", 35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m", 37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m", [all …]
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/linux-6.14.4/tools/include/linux/ |
D | bitops.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 31 * Defined here because those may be needed by architecture-specific static 52 #include <asm-generic/bitops.h> 54 #define for_each_set_bit(bit, addr, size) \ argument 55 for ((bit) = find_first_bit((addr), (size)); \ 56 (bit) < (size); \ 57 (bit) = find_next_bit((addr), (size), (bit) + 1)) 59 #define for_each_clear_bit(bit, addr, size) \ argument 60 for ((bit) = find_first_zero_bit((addr), (size)); \ 61 (bit) < (size); \ [all …]
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/linux-6.14.4/drivers/pinctrl/bcm/ |
D | pinctrl-iproc-gpio.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2014-2017 Broadcom 9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic 30 #include <linux/pinctrl/pinconf-generic.h> 34 #include "../pinctrl-utils.h" 68 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) 125 * Mapping from PINCONF pins to GPIO pins is 1-to-1 133 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a 145 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in iproc_set_bit() local 148 val = readl(chip->base + offset); in iproc_set_bit() [all …]
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/linux-6.14.4/drivers/bus/ |
D | qcom-ebi2.c | 1 // SPDX-License-Identifier: GPL-2.0-only 26 * CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit. 28 #define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1) 29 #define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3) 30 #define EBI2_CS2_ENABLE_MASK BIT(4) 31 #define EBI2_CS3_ENABLE_MASK BIT(5) 32 #define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7) 33 #define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9) 41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the 42 * memory continues to drive the data bus after OE is de-asserted. [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/clock/ti/ |
D | ti,divider-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Tero Kristo <[email protected]> 13 This clock It assumes a register-mapped adjustable clock rate divider 25 ti,index-starts-at-one - valid divisor values start at 1, not the default 32 ti,index-power-of-two - valid divisor values are powers of two. E.g: 49 Any zero value in this array means the corresponding bit-value is invalid 54 the number of bits to shift that mask, if necessary. If the shift value [all …]
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/linux-6.14.4/tools/testing/shared/ |
D | shared.mk | 1 # SPDX-License-Identifier: GPL-2.0 3 CFLAGS += -I../shared -I. -I../../include -I../../../lib -g -Og -Wall \ 4 -D_LGPL_SOURCE -fsanitize=address -fsanitize=undefined 5 LDFLAGS += -fsanitize=address -fsanitize=undefined 6 LDLIBS += -lpthread -lurcu 8 SHARED_OFILES = xarray-shared.o radix-tree.o idr.o linux.o $(LIBS) 10 SHARED_DEPS = Makefile ../shared/shared.mk ../shared/*.h generated/map-shift.h \ 11 generated/bit-length.h generated/autoconf.h \ 16 ../../../include/linux/radix-tree.h \ 17 ../../../lib/radix-tree.h \ [all …]
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/linux-6.14.4/sound/soc/sprd/ |
D | sprd-mcdt.c | 1 // SPDX-License-Identifier: GPL-2.0 14 #include "sprd-mcdt.h" 121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update() 125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update() 155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local 158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); in sprd_mcdt_dac_dma_enable() 160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); in sprd_mcdt_dac_dma_enable() 167 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(channel), BIT(channel)); in sprd_mcdt_adc_dma_enable() 169 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(channel)); in sprd_mcdt_adc_dma_enable() 176 sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, BIT(channel), in sprd_mcdt_ap_int_enable() [all …]
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