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/linux-6.14.4/drivers/net/ethernet/xilinx/
Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
73 /* Axi DMA Register definitions */
148 /* Axi Ethernet registers definition */
151 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
181 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
182 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
188 /* Bit Masks for Axi Ethernet RAF register */
207 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
[all …]
/linux-6.14.4/arch/arc/plat-axs10x/
Daxs10x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
11 #include <asm/asm-offsets.h>
33 * --------------------- in axs10x_enable_gpio_intc_wire()
34 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
35 * --------------------- in axs10x_enable_gpio_intc_wire()
37 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
38 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
39 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
43 * ------------------------ in axs10x_enable_gpio_intc_wire()
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/linux-6.14.4/Documentation/devicetree/bindings/net/
Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
22 - Radhey Shyam Pandey <[email protected]>
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/linux-6.14.4/drivers/clk/baikal-t1/
Dclk-ccu-div.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers clock driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
18 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/bt1-ccu.h>
28 #include "ccu-div.h"
29 #include "ccu-rst.h"
62 .base = _base, \
74 .base = _base, \
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/linux-6.14.4/Documentation/devicetree/bindings/display/imx/
Dfsl-imx-drm.txt8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,imx-display-subsystem";
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
25 - imx51
26 - imx53
27 - imx6q
28 - imx6qp
29 - reg: should be register base and length as documented in the
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Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <[email protected]>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
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/linux-6.14.4/sound/soc/adi/
Daxi-spdif.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <[email protected]>
66 return -EINVAL; in axi_spdif_trigger()
69 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_trigger()
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
98 rate * 64 * 2) - 1; in axi_spdif_hw_params()
101 regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat); in axi_spdif_hw_params()
102 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_hw_params()
112 snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL); in axi_spdif_dai_probe()
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Daxi-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <[email protected]>
63 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_trigger()
80 return -EINVAL; in axi_i2s_trigger()
83 regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val); in axi_i2s_trigger()
97 word_size = AXI_I2S_BITS_PER_FRAME / 2 - 1; in axi_i2s_hw_params()
98 bclk_div = DIV_ROUND_UP(clk_get_rate(i2s->clk_ref), bclk_rate) / 2 - 1; in axi_i2s_hw_params()
100 regmap_write(i2s->regmap, AXI_I2S_REG_CLK_CTRL, (word_size << 16) | in axi_i2s_hw_params()
113 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_startup()
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/linux-6.14.4/drivers/media/platform/renesas/rzg2l-cru/
Drzg2l-cru-regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * rzg2l-cru-regs.h--RZ/G2L (and alike SoCs) CRU Registers Definitions
29 /* Memory Bank Base Address (Lower) Register for CRU Image Data */
32 /* Memory Bank Base Address (Higher) Register for CRU Image Data */
43 /* AXI Master Transfer Setting Register for CRU Image Data */
48 /* AXI Master FIFO Pointer Register for CRU Image Data */
53 /* AXI Master Transfer Stop Register for CRU Image Data */
57 /* AXI Master Transfer Stop Status Register for CRU Image Data */
/linux-6.14.4/drivers/clk/microchip/
Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/microchip,mpfs-clock.h>
42 void __iomem *base; member
48 void __iomem *base; member
61 void __iomem *base; member
120 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
121 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
159 msspll_hw->base = data->msspll_base; in mpfs_clk_register_mssplls()
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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
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Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <[email protected]>
11 - Scott Branden <[email protected]>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
22 - brcm,iproc-pcie
23 # for the second generation of PAXB-based controllers, used in
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/linux-6.14.4/drivers/pci/controller/cadence/
Dpcie-cadence.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
117 (((aperture) - 2) << ((bar) * 8))
150 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
155 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
163 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
190 /* Region r AXI Region Base Address Register 0 */
195 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
197 /* Region r AXI Region Base Address Register 1 */
[all …]
/linux-6.14.4/drivers/iio/adc/
Dadi-axi-adc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices Generic AXI ADC IP core
6 * Copyright 2012-2020 Analog Devices Inc.
23 #include <linux/fpga/adi-axi-common.h>
26 #include <linux/iio/buffer-dmaengine.h>
96 guard(mutex)(&st->lock); in axi_adc_enable()
97 ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, in axi_adc_enable()
107 ret = regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_DRP_STATUS, in axi_adc_enable()
113 return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, in axi_adc_enable()
121 guard(mutex)(&st->lock); in axi_adc_disable()
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/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
19 static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) in dwmac1000_dma_axi() argument
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
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Dstmmac_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2011-2012 Vayavya Labs Pvt Ltd
12 #include <linux/clk-provider.h>
24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
25 plat->has_gmac = 1; in common_default_data()
26 plat->force_sf_dma_mode = 1; in common_default_data()
28 plat->mdio_bus_data->needs_reset = true; in common_default_data()
31 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
34 plat->unicast_filter_entries = 1; in common_default_data()
37 plat->maxmtu = JUMBO_LEN; in common_default_data()
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/linux-6.14.4/drivers/perf/
Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
60 #define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */
61 #define DDR_CAP_AXI_ID_FILTER_ENHANCED 0x3 /* support enhanced AXI ID filter */
62 #define DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER 0x4 /* support AXI ID PORT CHANNEL filter */
101 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
102 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
103 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
104 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
105 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
106 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
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/linux-6.14.4/drivers/iio/dac/
Dadi-axi-dac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices Generic AXI DAC IP core
6 * Copyright 2016-2024 Analog Devices Inc.
26 #include <linux/fpga/adi-axi-common.h>
28 #include <linux/iio/buffer-dmaengine.h>
32 #include "ad3552r-hs.h"
39 /* Base controls */
126 guard(mutex)(&st->lock); in axi_dac_enable()
127 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
136 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, in axi_dac_enable()
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/linux-6.14.4/drivers/clk/imx/
Dclk-imx6sll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2017-2018 NXP.
7 #include <dt-bindings/clock/imx6sll-clock.h>
10 #include <linux/clk-provider.h>
82 void __iomem *base; in imx6sll_clocks_init() local
89 clk_hw_data->num = IMX6SLL_CLK_END; in imx6sll_clocks_init()
90 hws = clk_hw_data->hws; in imx6sll_clocks_init()
101 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop"); in imx6sll_clocks_init()
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
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Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
33 static const char *gpu_axi_sels[] = { "axi", "ahb", };
34 static const char *pre_axi_sels[] = { "axi", "ahb", };
35 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m",…
51 static const char *pcie_axi_sels[] = { "axi", "ahb", };
56 static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
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Dclk-imx6ul.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
43 static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd0_720m", …
64 static const char *cko1_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "axi", "enfc", "dum…
131 void __iomem *base; in imx6ul_clocks_init() local
138 clk_hw_data->num = IMX6UL_CLK_END; in imx6ul_clocks_init()
139 hws = clk_hw_data->hws; in imx6ul_clocks_init()
150 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); in imx6ul_clocks_init()
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Dclk-imx8mp-audiomix.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/imx8mp-clock.h>
183 CLK_GATE_PARENT("ocrama", OCRAMA_IPG, "axi"),
189 CLK_GATE_PARENT("dsp", DSP_ROOT, "axi"),
190 CLK_GATE_PARENT("dspdbg", DSPDBG_ROOT, "axi"),
224 void __iomem *base; member
254 if (!of_property_present(dev->of_node, "#reset-cells")) in clk_imx8mp_audiomix_reset_controller_register()
259 return -ENOMEM; in clk_imx8mp_audiomix_reset_controller_register()
261 adev->name = "reset"; in clk_imx8mp_audiomix_reset_controller_register()
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/linux-6.14.4/Documentation/devicetree/bindings/media/
Dmarvell,mmp2-ccic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <[email protected]>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
26 power-domains:
30 $ref: /schemas/graph.yaml#/$defs/port-base
35 $ref: video-interfaces.yaml#
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/linux-6.14.4/drivers/clk/
Dclk-axi-clkgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AXI clkgen driver
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <[email protected]>
11 #include <linux/clk-provider.h>
58 void __iomem *base; member
144 d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); in axi_clkgen_calc_params()
145 d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()
148 fvco_min_fract = limits->fvco_min << fract_shift; in axi_clkgen_calc_params()
149 fvco_max_fract = limits->fvco_max << fract_shift; in axi_clkgen_calc_params()
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/linux-6.14.4/drivers/hwtracing/coresight/
Dcoresight-catu.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "coresight-priv.h"
13 /* Register offset from base */
41 * AXI - ARPROT bits:
42 * See AMBA AXI & ACE Protocol specification (ARM IHI 0022E)
45 * Bit 0: 0 - Unprivileged access, 1 - Privileged access
46 * Bit 1: 0 - Secure access, 1 - Non-secure access.
47 * Bit 2: 0 - Data access, 1 - instruction access.
65 void __iomem *base; member
74 return csdev_access_relaxed_read32(&drvdata->csdev->access, offset); \
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