Searched full:smmuv3 (Results 1 – 18 of 18) sorted by relevance
405 tristate "ARM Ltd. System MMU Version 3 (SMMUv3) Support"416 the ARM SMMUv3 architecture.420 bool "Shared Virtual Addressing support for the ARM SMMUv3"426 SMMUv3.432 bool "Enable IOMMUFD features for ARM SMMUv3 (EXPERIMENTAL)"451 bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3"454 Support for NVIDIA CMDQ-Virtualization extension for ARM SMMUv3. The
7 title: Arm SMMUv3 Performance Monitor Counter Group14 An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
434 * struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 nested STE439 * Allowed fields: (Refer to "5.2 Stream Table Entry" in SMMUv3 HW Spec)457 * @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table548 * struct iommu_hw_info_arm_smmuv3 - ARM SMMUv3 hardware information559 * from 6.3.1 to 6.3.6 in the SMMUv3 Spec.577 * compatibility with future kernels. Several features in the SMMUv3594 * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type734 * @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMMUv3778 * struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cache invalidation937 * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type[all …]
7 title: ARM SMMUv3 Architecture Implementation14 The SMMUv3 architecture is a significant departure from previous
137 tristate "ARM SMMUv3 Performance Monitors Extension"141 Provides support for the ARM SMMUv3 Performance Monitor Counter
5 * Monitor Counter Groups (PMCG) associated with an SMMUv3 node8 * SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where774 flags, "smmuv3-pmu", pmu); in smmu_pmu_setup_irq()1034 MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
22 #define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
418 * SMMUv3 dev ID mapping index was introduced in revision 1 in iort_get_id_mapping_index()1461 /* Retrieve SMMUv3 specific data */ in arm_smmu_v3_count_resources()1483 * irq line. Use single irq line for all the SMMUv3 interrupts. in arm_smmu_v3_is_combined_irq()1515 /* Retrieve SMMUv3 specific data */ in arm_smmu_v3_init_resources()1559 /* Retrieve SMMUv3 specific data */ in arm_smmu_v3_dma_configure()1565 /* We expect the dma masks to be equivalent for all SMMUv3 set-ups */ in arm_smmu_v3_dma_configure()1574 * set numa proximity domain for smmuv3 device
3 * IOMMU API for ARM architected SMMUv3 implementations.724 /* An SMMUv3 instance */
162 * struct tegra241_cmdqv - CMDQ-V for SMMUv3163 * @smmu: SMMUv3 device
3 * Implementation of the IOMMU SVA API for the ARM SMMUv3
3 * IOMMU API for ARM architected SMMUv3 implementations.4005 * lines. Use a single irq line for all the SMMUv3 interrupts. in arm_smmu_setup_irqs()4543 /* Retrieve SMMUv3 specific data */ in arm_smmu_device_acpi_probe()4828 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
370 * of HiSilicon platforms hip06/hip07 to support the SMMUv3376 * ARM SMMUv3 driver requires a quirk to treat the MSI regions
1219 * of HiSilicon platforms hip06/hip07 to support the SMMUv31225 * ARM SMMUv3 driver requires a quirk to treat the MSI regions
104 e.g. vSID of ARM SMMUv3, vDeviceID of AMD IOMMU, and vRID of Intel VT-d to a
604 u64 base_address; /* SMMUv3 base address */619 #define ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */620 #define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* hi_silicon Hi161x SMMUv3 */621 #define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */
231 | Cavium | ThunderX2 SMMUv3| #74 | N/A |233 | Cavium | ThunderX2 SMMUv3| #126 | N/A |
1287 * The PTT device is supposed to behind an ARM SMMUv3, which