Searched full:smmuv2 (Results 1 – 4 of 4) sorted by relevance
198 For SMMUv2 implementations, there must be exactly one interrupt per
583 #define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */587 #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium thunder_x SMMUv2 */
229 | Cavium | ThunderX SMMUv2 | #27704 | N/A |
526 * assume that only one of Intel, AMD, s390, PAMU or legacy SMMUv2 can in __iommu_probe_device()